NXP Semiconductors
MKM34ZA5
2024.06.02
MKM34ZA5 Freescale Microcontroller
CM0PLUS
r0p0
little
2
false
8
32
ADC
Analog-to-Digital Converter
ADC
0x0
0x0
0x60
registers
n
ADC
16
CFG1
ADC Configuration Register 1
0x10
32
read-write
n
0x0
0x0
ADICLK
Input Clock Select
0
2
read-write
00
Bus clock
#00
01
Bus clock divided by 2(BUSCLK/DIV2)
#01
10
Alternate clock (ALTCLK)
#10
11
Asynchronous clock (ADACK)
#11
ADIV
Clock Divide Select
5
2
read-write
00
The divide ratio is 1 and the clock rate is input clock.
#00
01
The divide ratio is 2 and the clock rate is (input clock)/2.
#01
10
The divide ratio is 4 and the clock rate is (input clock)/4.
#10
11
The divide ratio is 8 and the clock rate is (input clock)/8.
#11
ADLPC
Low-Power Configuration
7
1
read-write
0
Normal power configuration.
#0
1
Low-power configuration. The power is reduced at the expense of maximum clock speed.
#1
ADLSMP
Sample Time Configuration
4
1
read-write
0
Short sample time.
#0
1
Long sample time.
#1
MODE
Conversion mode selection
2
2
read-write
00
It is single-ended 8-bit conversion.
#00
01
It is single-ended 12-bit conversion .
#01
10
It is single-ended 10-bit conversion.
#10
11
It is single-ended 16-bit conversion..
#11
CFG2
ADC Configuration Register 2
0x14
32
read-write
n
0x0
0x0
ADACKEN
Asynchronous Clock Output Enable
3
1
read-write
0
Asynchronous clock output disabled; Asynchronous clock is enabled only if selected by ADICLK and a conversion is active.
#0
1
Asynchronous clock and clock output is enabled regardless of the state of the ADC.
#1
ADHSC
High-Speed Configuration
2
1
read-write
0
Normal conversion sequence selected.
#0
1
High-speed conversion sequence selected with 2 additional ADCK cycles to total conversion time.
#1
ADLSTS
Long Sample Time Select
0
2
read-write
00
Default longest sample time; 20 extra ADCK cycles; 24 ADCK cycles total.
#00
01
12 extra ADCK cycles; 16 ADCK cycles total sample time.
#01
10
6 extra ADCK cycles; 10 ADCK cycles total sample time.
#10
11
2 extra ADCK cycles; 6 ADCK cycles total sample time.
#11
MUXSEL
ADC Mux Select
4
1
read-write
0
ADxxa channels are selected.
#0
1
ADxxb channels are selected.
#1
CLP0
ADC Plus-Side General Calibration Value Register
0x5C
32
read-write
n
0x0
0x0
CLP0
Calibration Value
0
6
read-write
CLP1
ADC Plus-Side General Calibration Value Register
0x58
32
read-write
n
0x0
0x0
CLP1
Calibration Value
0
7
read-write
CLP2
ADC Plus-Side General Calibration Value Register
0x54
32
read-write
n
0x0
0x0
CLP2
Calibration Value
0
8
read-write
CLP3
ADC Plus-Side General Calibration Value Register
0x50
32
read-write
n
0x0
0x0
CLP3
Calibration Value
0
9
read-write
CLP4
ADC Plus-Side General Calibration Value Register
0x4C
32
read-write
n
0x0
0x0
CLP4
Calibration Value
0
10
read-write
CLPD
ADC Plus-Side General Calibration Value Register
0x44
32
read-write
n
0x0
0x0
CLPD
Calibration Value
0
6
read-write
CLPS
ADC Plus-Side General Calibration Value Register
0x48
32
read-write
n
0x0
0x0
CLPS
Calibration Value
0
6
read-write
CV1
Compare Value Registers
0x50
32
read-write
n
0x0
0x0
CV
Compare Value.
0
16
read-write
CV2
Compare Value Registers
0x7C
32
read-write
n
0x0
0x0
CV
Compare Value.
0
16
read-write
OFS
ADC Offset Correction Register
0x38
32
read-write
n
0x0
0x0
OFS
Offset Error Correction Value
0
16
read-write
PG
ADC Plus-Side Gain Register
0x3C
32
read-write
n
0x0
0x0
PG
Plus-Side Gain
0
16
read-write
RA
ADC Data Result Register
0x30
32
read-only
n
0x0
0x0
D
Data result
0
16
read-only
RB
ADC Data Result Register
0x4C
32
read-only
n
0x0
0x0
D
Data result
0
16
read-only
RC
ADC Data Result Register
0x6C
32
read-only
n
0x0
0x0
D
Data result
0
16
read-only
RD
ADC Data Result Register
0x90
32
read-only
n
0x0
0x0
D
Data result
0
16
read-only
SC1A
ADC Status and Control Registers 1
0x0
32
read-write
n
0x0
0x0
ADCH
Input channel select
0
5
read-write
00000
AD0 is selected as input.
#00000
00001
AD1 is selected as input.
#00001
00010
AD2 is selected as input.
#00010
00011
AD3 is selected as input.
#00011
00100
AD4 is selected as input.
#00100
00101
AD5 is selected as input.
#00101
00110
AD6 is selected as input.
#00110
00111
AD7 is selected as input.
#00111
01000
AD8 is selected as input.
#01000
01001
AD9 is selected as input.
#01001
01010
AD10 is selected as input.
#01010
01011
AD11 is selected as input.
#01011
01100
AD12 is selected as input.
#01100
01101
AD13 is selected as input.
#01101
01110
AD14 is selected as input.
#01110
01111
AD15 is selected as input.
#01111
10000
AD16 is selected as input.
#10000
10001
AD17 is selected as input.
#10001
10010
AD18 is selected as input.
#10010
10011
AD19 is selected as input.
#10011
10100
AD20 is selected as input.
#10100
10101
AD21 is selected as input.
#10101
10110
AD22 is selected as input.
#10110
10111
AD23 is selected as input.
#10111
11010
Temp Sensor (single-ended) is selected as input.
#11010
11011
Bandgap (single-ended) is selected as input.
#11011
11101
VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL].
#11101
11110
VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL].
#11110
11111
Module is disabled.
#11111
AIEN
Interrupt Enable
6
1
read-write
0
Conversion complete interrupt is disabled.
#0
1
Conversion complete interrupt is enabled.
#1
COCO
Conversion Complete Flag
7
1
read-only
0
Conversion is not completed.
#0
1
Conversion is completed.
#1
SC1B
ADC Status and Control Registers 1
0x4
32
read-write
n
0x0
0x0
ADCH
Input channel select
0
5
read-write
00000
AD0 is selected as input.
#00000
00001
AD1 is selected as input.
#00001
00010
AD2 is selected as input.
#00010
00011
AD3 is selected as input.
#00011
00100
AD4 is selected as input.
#00100
00101
AD5 is selected as input.
#00101
00110
AD6 is selected as input.
#00110
00111
AD7 is selected as input.
#00111
01000
AD8 is selected as input.
#01000
01001
AD9 is selected as input.
#01001
01010
AD10 is selected as input.
#01010
01011
AD11 is selected as input.
#01011
01100
AD12 is selected as input.
#01100
01101
AD13 is selected as input.
#01101
01110
AD14 is selected as input.
#01110
01111
AD15 is selected as input.
#01111
10000
AD16 is selected as input.
#10000
10001
AD17 is selected as input.
#10001
10010
AD18 is selected as input.
#10010
10011
AD19 is selected as input.
#10011
10100
AD20 is selected as input.
#10100
10101
AD21 is selected as input.
#10101
10110
AD22 is selected as input.
#10110
10111
AD23 is selected as input.
#10111
11010
Temp Sensor (single-ended) is selected as input.
#11010
11011
Bandgap (single-ended) is selected as input.
#11011
11101
VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL].
#11101
11110
VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL].
#11110
11111
Module is disabled.
#11111
AIEN
Interrupt Enable
6
1
read-write
0
Conversion complete interrupt is disabled.
#0
1
Conversion complete interrupt is enabled.
#1
COCO
Conversion Complete Flag
7
1
read-only
0
Conversion is not completed.
#0
1
Conversion is completed.
#1
SC1C
ADC Status and Control Registers 1
0xC
32
read-write
n
0x0
0x0
ADCH
Input channel select
0
5
read-write
00000
AD0 is selected as input.
#00000
00001
AD1 is selected as input.
#00001
00010
AD2 is selected as input.
#00010
00011
AD3 is selected as input.
#00011
00100
AD4 is selected as input.
#00100
00101
AD5 is selected as input.
#00101
00110
AD6 is selected as input.
#00110
00111
AD7 is selected as input.
#00111
01000
AD8 is selected as input.
#01000
01001
AD9 is selected as input.
#01001
01010
AD10 is selected as input.
#01010
01011
AD11 is selected as input.
#01011
01100
AD12 is selected as input.
#01100
01101
AD13 is selected as input.
#01101
01110
AD14 is selected as input.
#01110
01111
AD15 is selected as input.
#01111
10000
AD16 is selected as input.
#10000
10001
AD17 is selected as input.
#10001
10010
AD18 is selected as input.
#10010
10011
AD19 is selected as input.
#10011
10100
AD20 is selected as input.
#10100
10101
AD21 is selected as input.
#10101
10110
AD22 is selected as input.
#10110
10111
AD23 is selected as input.
#10111
11010
Temp Sensor (single-ended) is selected as input.
#11010
11011
Bandgap (single-ended) is selected as input.
#11011
11101
VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL].
#11101
11110
VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL].
#11110
11111
Module is disabled.
#11111
AIEN
Interrupt Enable
6
1
read-write
0
Conversion complete interrupt is disabled.
#0
1
Conversion complete interrupt is enabled.
#1
COCO
Conversion Complete Flag
7
1
read-only
0
Conversion is not completed.
#0
1
Conversion is completed.
#1
SC1D
ADC Status and Control Registers 1
0x18
32
read-write
n
0x0
0x0
ADCH
Input channel select
0
5
read-write
00000
AD0 is selected as input.
#00000
00001
AD1 is selected as input.
#00001
00010
AD2 is selected as input.
#00010
00011
AD3 is selected as input.
#00011
00100
AD4 is selected as input.
#00100
00101
AD5 is selected as input.
#00101
00110
AD6 is selected as input.
#00110
00111
AD7 is selected as input.
#00111
01000
AD8 is selected as input.
#01000
01001
AD9 is selected as input.
#01001
01010
AD10 is selected as input.
#01010
01011
AD11 is selected as input.
#01011
01100
AD12 is selected as input.
#01100
01101
AD13 is selected as input.
#01101
01110
AD14 is selected as input.
#01110
01111
AD15 is selected as input.
#01111
10000
AD16 is selected as input.
#10000
10001
AD17 is selected as input.
#10001
10010
AD18 is selected as input.
#10010
10011
AD19 is selected as input.
#10011
10100
AD20 is selected as input.
#10100
10101
AD21 is selected as input.
#10101
10110
AD22 is selected as input.
#10110
10111
AD23 is selected as input.
#10111
11010
Temp Sensor (single-ended) is selected as input.
#11010
11011
Bandgap (single-ended) is selected as input.
#11011
11101
VREFSH is selected as input. Voltage reference selected is determined by SC2[REFSEL].
#11101
11110
VREFSL is selected as input. Voltage reference selected is determined by SC2[REFSEL].
#11110
11111
Module is disabled.
#11111
AIEN
Interrupt Enable
6
1
read-write
0
Conversion complete interrupt is disabled.
#0
1
Conversion complete interrupt is enabled.
#1
COCO
Conversion Complete Flag
7
1
read-only
0
Conversion is not completed.
#0
1
Conversion is completed.
#1
SC2
Status and Control Register 2
0x30
32
read-write
n
0x0
0x0
ACFE
Compare Function Enable
5
1
read-write
0
Compare function disabled.
#0
1
Compare function enabled.
#1
ACFGT
Compare Function Greater Than Enable
4
1
read-write
0
Configures less than threshold, outside range not inclusive and inside range not inclusive; functionality based on the values placed in CV1 and CV2.
#0
1
Configures greater than or equal to threshold, outside and inside ranges inclusive; functionality based on the values placed in CV1 and CV2.
#1
ACREN
Compare Function Range Enable
3
1
read-write
0
Range function disabled. Only CV1 is compared.
#0
1
Range function enabled. Both CV1 and CV2 are compared.
#1
ADACT
Conversion Active
7
1
read-only
0
Conversion not in progress.
#0
1
Conversion in progress.
#1
ADTRG
Conversion Trigger Select
6
1
read-write
0
Software trigger selected.
#0
1
Hardware trigger selected.
#1
DMAEN
DMA Enable
2
1
read-write
0
DMA is disabled.
#0
1
DMA is enabled and will assert the ADC DMA request during an ADC conversion complete event noted when any of the SC1n[COCO] flags is asserted.
#1
REFSEL
Voltage Reference Selection
0
2
read-write
00
Default voltage reference pin pair, that is, external pins VREFH and VREFL
#00
01
Alternate reference pair, that is, VALTH and VALTL . This pair may be additional external pins or internal sources depending on the MCU configuration. See the chip configuration information for details specific to this MCU
#01
10
Internal bandgap reference and associated ground reference (V BGH and V BGL ). Consult the Chip Configuration information for details specific to this MCU.
#10
SC3
Status and Control Register 3
0x34
32
read-write
n
0x0
0x0
ADCO
Continuous Conversion Enable
3
1
read-write
0
One conversion or one set of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
#0
1
Continuous conversions or sets of conversions if the hardware average function is enabled, that is, AVGE=1, after initiating a conversion.
#1
AVGE
Hardware Average Enable
2
1
read-write
0
Hardware average function disabled.
#0
1
Hardware average function enabled.
#1
AVGS
Hardware Average Select
0
2
read-write
00
4 samples averaged.
#00
01
8 samples averaged.
#01
10
16 samples averaged.
#10
11
32 samples averaged.
#11
CAL
Calibration
7
1
read-write
CALF
Calibration Failed Flag
6
1
read-only
0
Calibration completed normally.
#0
1
Calibration failed. ADC accuracy specifications are not guaranteed.
#1
AFE
This section describes the ADC registers.
AFE
0x0
0x0
0x60
registers
n
AFE_CH0
21
AFE_CH1
22
AFE_CH2
23
AFE_CH3
24
CH0_CFR
Channel0 Configuration Register
0x0
32
read-write
n
0x0
0x0
BYP_MODE
AFE Channel0 bypass mode
17
1
read-write
0
Normal mode
#0
1
Bypass mode where ADC and PGA of channel0 are disabled.
#1
CC
Continuous Conversion/Single Conversion Mode Select
12
1
read-write
0
One conversion following a triggering event
#0
1
Continuous conversions following a triggering event.
#1
DEC_CLK_EDGE_SEL
Decimator Clock Edge Select
11
1
read-write
0
Posedge will be used.
#0
1
Negedge will be used.
#1
DEC_CLK_INP_SEL
Decimator Clock Input Select
10
1
read-write
0
On the chip modulator clock will be used
#0
1
External clock will be used.
#1
DEC_EN
Decimation Filter enable
13
1
read-write
0
Decimation filter is disabled.
#0
1
Decimation filter is enabled.
#1
DEC_OSR
Decimator OverSampling Ratio select
29
3
read-write
000
64
#000
001
128
#001
010
256
#010
011
512
#011
100
1024
#100
101
2048
#101
HW_TRG
Hardware Trigger Select
9
1
read-write
0
Software trigger select
#0
1
Hardware trigger select
#1
PGA_EN
PGA enable
24
1
read-write
0
PGA disabled
#0
1
PGA enabled
#1
PGA_GAIN_SEL
PGA Gain Select
19
3
read-write
001
1x (default)
#001
010
2x
#010
011
4x
#011
100
8x
#100
101
16x
#101
110
32x
#110
SD_MOD_EN
Sigma Delta Modulator enable
14
1
read-write
0
SD ADC1 is disabled
#0
1
SD ADC1 is enabled
#1
CH0_DR
Channel0 Delay Register
0x2C
32
read-write
n
0x0
0x0
DLY
Delay
0
11
read-write
CH0_RR
Channel0 Result Register
0x44
32
read-only
n
0x0
0x0
SDR
Sample Data Result
0
23
read-only
SIGN_BITS
Sign Bits
23
9
read-only
CH1_CFR
Channel1 Configuration Register
0x4
32
read-write
n
0x0
0x0
BYP_MODE
AFE Channel1 bypass mode
17
1
read-write
0
Normal mode
#0
1
Bypass mode where ADC and PGA of channel1 are disabled.
#1
CC
Continuous Conversion/Single Conversion Mode Select
12
1
read-write
0
One conversion following a triggering event
#0
1
Continuous conversions following a triggering event.
#1
DEC_CLK_EDGE_SEL
Decimator Clock Edge Select
11
1
read-write
0
Posedge will be used.
#0
1
Negedge will be used.
#1
DEC_CLK_INP_SEL
Decimator Clock Input Select
10
1
read-write
0
On the chip modulator clock will be used
#0
1
External clock will be used.
#1
DEC_EN
Decimation Filter enable
13
1
read-write
0
Decimation filter is disabled.
#0
1
Decimation filter is enabled.
#1
DEC_OSR
Decimator OverSampling Ratio select
29
3
read-write
000
64
#000
001
128
#001
010
256
#010
011
512
#011
100
1024
#100
101
2048
#101
HW_TRG
Hardware Trigger Select
9
1
read-write
0
Software trigger select
#0
1
Hardware trigger select
#1
PGA_EN
PGA enable
24
1
read-write
0
PGA disabled
#0
1
PGA enabled
#1
PGA_GAIN_SEL
PGA Gain Select
19
3
read-write
001
1x (default)
#001
010
2x
#010
011
4x
#011
100
8x
#100
101
16x
#101
110
32x
#110
SD_MOD_EN
Sigma Delta Modulator enable
14
1
read-write
0
SD ADC1 is disabled
#0
1
SD ADC1 is enabled
#1
CH1_DR
Channel1 Delay Register
0x30
32
read-write
n
0x0
0x0
DLY
Delay
0
11
read-write
CH1_RR
Channel1 Result Register
0x48
32
read-only
n
0x0
0x0
SDR
Sample Data Result
0
23
read-only
SIGN_BITS
Sign Bits
23
9
read-only
CH2_CFR
Channel2 Configuration Register
0x8
32
read-write
n
0x0
0x0
BYP_MODE
AFE Channel2 bypass mode
17
1
read-write
0
Normal mode
#0
1
Bypass mode where ADC and PGA of channel2 are disabled.
#1
CC
Continuous Conversion/Single Conversion Mode Select
12
1
read-write
0
One conversion following a triggering event
#0
1
Continuous conversions following a triggering event.
#1
DEC_CLK_EDGE_SEL
Decimator Clock Edge Select
11
1
read-write
0
Posedge will be used.
#0
1
Negedge will be used.
#1
DEC_CLK_INP_SEL
Decimator Clock Input Select
10
1
read-write
0
On the chip modulator clock will be used.
#0
1
External clock will be used.
#1
DEC_EN
Decimation Filter enable
13
1
read-write
0
Decimation filter is disabled.
#0
1
Decimation filter is enabled.
#1
DEC_OSR
Decimator OverSampling Ratio select
29
3
read-write
000
64
#000
001
128
#001
010
256
#010
011
512
#011
100
1024
#100
101
2048
#101
HW_TRG
Hardware Trigger Select
9
1
read-write
0
Software trigger select
#0
1
Hardware trigger select
#1
SD_MOD_EN
Sigma Delta Modulator enable
14
1
read-write
0
SD ADC3 is disabled
#0
1
SD ADC3 is enabled
#1
CH2_DR
Channel2 Delay Register
0x34
32
read-write
n
0x0
0x0
DLY
Delay
0
11
read-write
CH2_RR
Channel2 Result Register
0x4C
32
read-only
n
0x0
0x0
SDR
Sample Data result
0
23
read-only
SIGN_BITS
Sign Bits
23
9
read-only
CH3_CFR
Channel3 Configuration Register
0xC
32
read-write
n
0x0
0x0
BYP_MODE
AFE Channel3 bypass mode
17
1
read-write
0
Normal mode
#0
1
Bypass mode where ADC and PGA of channel3 are disabled.
#1
CC
Continuous Conversion/Single Conversion Mode Select
12
1
read-write
0
One conversion following a triggering event
#0
1
Continuous conversions following a triggering event.
#1
DEC_CLK_EDGE_SEL
Decimator Clock Edge Select
11
1
read-write
0
Posedge will be used.
#0
1
Negedge will be used.
#1
DEC_CLK_INP_SEL
Decimator Clock Input Select
10
1
read-write
0
On the chip modulator clock will be used.
#0
1
External clock will be used.
#1
DEC_EN
Decimation Filter enable
13
1
read-write
0
Decimation filter is disabled.
#0
1
Decimation filter is enabled.
#1
DEC_OSR
Decimator OverSampling Ratio select
29
3
read-write
000
64
#000
001
128
#001
010
256
#010
011
512
#011
100
1024
#100
101
2048
#101
HW_TRG
Hardware Trigger Select
9
1
read-write
0
Software trigger select
#0
1
Hardware trigger select
#1
SD_MOD_EN
Sigma Delta Modulator enable
14
1
read-write
0
SD ADC3 is disabled
#0
1
SD ADC3 is enabled
#1
CH3_DR
Channel3 Delay Register
0x38
32
read-write
n
0x0
0x0
DLY
Delay
0
11
read-write
CH3_RR
Channel3 Result Register
0x50
32
read-only
n
0x0
0x0
SDR
Sample Data result
0
23
read-only
SIGN_BITS
Sign Bits
23
9
read-only
CKR
Clock Configuration Register
0x1C
32
read-write
n
0x0
0x0
CLS
Clock Source Select
21
2
read-write
00
mod_clk0
#00
01
mod_clk1
#01
10
mod_clk2
#10
11
mod_clk3
#11
DIV
Clock Divider Select
28
4
read-write
0000
divide by 1
#0000
0001
divide by 2 (default)
#0001
0010
divide by 4
#0010
0011
divide by 8
#0011
0100
divide by 16
#0100
0101
divide by 32
#0101
0110
divide by 64
#0110
0111
divide by 128
#0111
1xxx
divide by 256
#1xxx
CR
Control Register
0x18
32
read-write
n
0x0
0x0
DLY_OK
Delay OK
21
1
write-only
LPM_EN
Low power Mode enable
25
1
read-write
0
AFE will be in normal mode
#0
1
AFE will be in low power mode. Setting this bit reduce the current consumption of ADC and Buffer Amplifier , the max modulator clock frequency is below 1Mhz.
#1
MSTR_EN
AFE Master Enable
31
1
read-write
0
All ADCs are disabled.
#0
1
All ADCs and filters will get simultaneously enabled .
#1
RESULT_FORMAT
Result Format
18
1
read-write
0
Left justified 2's complement 32-bit : SVVVVVVVVVVVVVVVVVVVVVVV00000000 where (S= sign bit , V=valid result value, 0=zero)
#0
1
Right justified 2's complement 32-bit : SSSSSSSSSVVVVVVVVVVVVVVVVVVVVVVV where (S= sign bit , V= valid result value, 0= zero)
#1
RST_B
Software Reset
22
1
read-write
0
All ADCs, PGAs and Decimation filters are disabled. Clock Configuration bits will be reset.
#0
1
.= All ADCs, PGAs and Decimation filters are enabled.
#1
SOFT_TRG0
Software Trigger0
30
1
write-only
SOFT_TRG1
Software Trigger1
29
1
write-only
SOFT_TRG2
Software Trigger2
28
1
write-only
SOFT_TRG3
Software Trigger3
27
1
write-only
STRTUP_CNT
Start up count
9
7
read-write
DI
DMA and Interrupt Register
0x20
32
read-write
n
0x0
0x0
DMAEN0
DMA Enable0
31
1
read-write
DMAEN1
DMA Enable1
30
1
read-write
DMAEN2
DMA Enable2
29
1
read-write
DMAEN3
DMA Enable3
28
1
read-write
INTEN0
Interrupt Enable 0
26
1
read-write
INTEN1
Interrupt Enable 1
25
1
read-write
INTEN2
Interrupt Enable 2
24
1
read-write
INTEN3
Interrupt Enable 3
23
1
read-write
SR
Status Register
0x5C
32
read-only
n
0x0
0x0
COC0
Conversion Complete
31
1
read-only
COC1
Conversion Complete
30
1
read-only
COC2
Conversion Complete
29
1
read-only
COC3
Conversion Complete
28
1
read-only
OVR0
Overflow Flag
24
1
read-only
OVR1
Overflow Flag
23
1
read-only
OVR2
Overflow Flag
22
1
read-only
OVR3
Overflow Flag
21
1
read-only
RDY0
AFE Ready1
19
1
read-only
0
AFE Channel0 is disabled or has not completed its start up period
#0
1
AFE Channel0 is ready to initiate conversions.
#1
RDY1
AFE Ready2
18
1
read-only
0
AFE Channel1 is disabled or has not completed its start up period
#0
1
AFE Channel1 is ready to initiate conversions.
#1
RDY2
AFE Ready3
17
1
read-only
0
AFE Channel2 is disabled or has not completed its start up period
#0
1
AFE Channel2 is ready to initiate conversions.
#1
RDY3
AFE Ready4
16
1
read-only
0
AFE Channel3 is disabled or has not completed its start up period
#0
1
AFE Channel3 is ready to initiate conversions.
#1
AIPS
AIPS-Lite Bridge
AIPS
0x0
0x20
0x50
registers
n
PACRA
Peripheral Access Control Register
0x20
32
read-write
n
0x0
0x0
AC0
Attribute Check
28
3
read-write
AC1
Attribute Check
24
3
read-write
AC2
Attribute Check
20
3
read-write
AC3
Attribute Check
16
3
read-write
AC4
Attribute Check
12
3
read-write
AC5
Attribute Check
8
3
read-write
AC6
Attribute Check
4
3
read-write
AC7
Attribute Check
0
3
read-write
RO0
Read Only
31
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO1
Read Only
27
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO2
Read Only
23
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO3
Read Only
19
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO4
Read Only
15
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO5
Read Only
11
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO6
Read Only
7
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO7
Read Only
3
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
PACRB
Peripheral Access Control Register
0x24
32
read-write
n
0x0
0x0
AC0
Attribute Check
28
3
read-write
AC1
Attribute Check
24
3
read-write
AC2
Attribute Check
20
3
read-write
AC3
Attribute Check
16
3
read-write
AC4
Attribute Check
12
3
read-write
AC5
Attribute Check
8
3
read-write
AC6
Attribute Check
4
3
read-write
AC7
Attribute Check
0
3
read-write
RO0
Read Only
31
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO1
Read Only
27
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO2
Read Only
23
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO3
Read Only
19
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO4
Read Only
15
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO5
Read Only
11
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO6
Read Only
7
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO7
Read Only
3
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
PACRE
Peripheral Access Control Register
0x40
32
read-write
n
0x0
0x0
AC0
Attribute Check
28
3
read-write
AC1
Attribute Check
24
3
read-write
AC2
Attribute Check
20
3
read-write
AC3
Attribute Check
16
3
read-write
AC4
Attribute Check
12
3
read-write
AC5
Attribute Check
8
3
read-write
AC6
Attribute Check
4
3
read-write
AC7
Attribute Check
0
3
read-write
RO0
Read Only
31
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO1
Read Only
27
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO2
Read Only
23
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO3
Read Only
19
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO4
Read Only
15
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO5
Read Only
11
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO6
Read Only
7
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO7
Read Only
3
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
PACRF
Peripheral Access Control Register
0x44
32
read-write
n
0x0
0x0
AC0
Attribute Check
28
3
read-write
AC1
Attribute Check
24
3
read-write
AC2
Attribute Check
20
3
read-write
AC3
Attribute Check
16
3
read-write
AC4
Attribute Check
12
3
read-write
AC5
Attribute Check
8
3
read-write
AC6
Attribute Check
4
3
read-write
AC7
Attribute Check
0
3
read-write
RO0
Read Only
31
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO1
Read Only
27
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO2
Read Only
23
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO3
Read Only
19
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO4
Read Only
15
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO5
Read Only
11
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO6
Read Only
7
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO7
Read Only
3
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
PACRG
Peripheral Access Control Register
0x48
32
read-write
n
0x0
0x0
AC0
Attribute Check
28
3
read-write
AC1
Attribute Check
24
3
read-write
AC2
Attribute Check
20
3
read-write
AC3
Attribute Check
16
3
read-write
AC4
Attribute Check
12
3
read-write
AC5
Attribute Check
8
3
read-write
AC6
Attribute Check
4
3
read-write
AC7
Attribute Check
0
3
read-write
RO0
Read Only
31
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO1
Read Only
27
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO2
Read Only
23
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO3
Read Only
19
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO4
Read Only
15
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO5
Read Only
11
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO6
Read Only
7
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO7
Read Only
3
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
PACRH
Peripheral Access Control Register
0x4C
32
read-write
n
0x0
0x0
AC0
Attribute Check
28
3
read-write
AC1
Attribute Check
24
3
read-write
AC2
Attribute Check
20
3
read-write
AC3
Attribute Check
16
3
read-write
AC4
Attribute Check
12
3
read-write
AC5
Attribute Check
8
3
read-write
AC6
Attribute Check
4
3
read-write
AC7
Attribute Check
0
3
read-write
RO0
Read Only
31
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO1
Read Only
27
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO2
Read Only
23
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO3
Read Only
19
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO4
Read Only
15
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO5
Read Only
11
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO6
Read Only
7
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO7
Read Only
3
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
PACRI
Peripheral Access Control Register
0x50
32
read-write
n
0x0
0x0
AC0
Attribute Check
28
3
read-write
AC1
Attribute Check
24
3
read-write
AC2
Attribute Check
20
3
read-write
AC3
Attribute Check
16
3
read-write
AC4
Attribute Check
12
3
read-write
AC5
Attribute Check
8
3
read-write
AC6
Attribute Check
4
3
read-write
AC7
Attribute Check
0
3
read-write
RO0
Read Only
31
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO1
Read Only
27
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO2
Read Only
23
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO3
Read Only
19
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO4
Read Only
15
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO5
Read Only
11
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO6
Read Only
7
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO7
Read Only
3
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
PACRJ
Peripheral Access Control Register
0x54
32
read-write
n
0x0
0x0
AC0
Attribute Check
28
3
read-write
AC1
Attribute Check
24
3
read-write
AC2
Attribute Check
20
3
read-write
AC3
Attribute Check
16
3
read-write
AC4
Attribute Check
12
3
read-write
AC5
Attribute Check
8
3
read-write
AC6
Attribute Check
4
3
read-write
AC7
Attribute Check
0
3
read-write
RO0
Read Only
31
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO1
Read Only
27
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO2
Read Only
23
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO3
Read Only
19
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO4
Read Only
15
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO5
Read Only
11
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO6
Read Only
7
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO7
Read Only
3
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
PACRK
Peripheral Access Control Register
0x58
32
read-write
n
0x0
0x0
AC0
Attribute Check
28
3
read-write
AC1
Attribute Check
24
3
read-write
AC2
Attribute Check
20
3
read-write
AC3
Attribute Check
16
3
read-write
AC4
Attribute Check
12
3
read-write
AC5
Attribute Check
8
3
read-write
AC6
Attribute Check
4
3
read-write
AC7
Attribute Check
0
3
read-write
RO0
Read Only
31
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO1
Read Only
27
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO2
Read Only
23
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO3
Read Only
19
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO4
Read Only
15
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO5
Read Only
11
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO6
Read Only
7
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO7
Read Only
3
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
PACRL
Peripheral Access Control Register
0x5C
32
read-write
n
0x0
0x0
AC0
Attribute Check
28
3
read-write
AC1
Attribute Check
24
3
read-write
AC2
Attribute Check
20
3
read-write
AC3
Attribute Check
16
3
read-write
AC4
Attribute Check
12
3
read-write
AC5
Attribute Check
8
3
read-write
AC6
Attribute Check
4
3
read-write
AC7
Attribute Check
0
3
read-write
RO0
Read Only
31
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO1
Read Only
27
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO2
Read Only
23
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO3
Read Only
19
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO4
Read Only
15
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO5
Read Only
11
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO6
Read Only
7
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO7
Read Only
3
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
PACRM
Peripheral Access Control Register
0x60
32
read-write
n
0x0
0x0
AC0
Attribute Check
28
3
read-write
AC1
Attribute Check
24
3
read-write
AC2
Attribute Check
20
3
read-write
AC3
Attribute Check
16
3
read-write
AC4
Attribute Check
12
3
read-write
AC5
Attribute Check
8
3
read-write
AC6
Attribute Check
4
3
read-write
AC7
Attribute Check
0
3
read-write
RO0
Read Only
31
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO1
Read Only
27
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO2
Read Only
23
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO3
Read Only
19
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO4
Read Only
15
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO5
Read Only
11
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO6
Read Only
7
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO7
Read Only
3
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
PACRN
Peripheral Access Control Register
0x64
32
read-write
n
0x0
0x0
AC0
Attribute Check
28
3
read-write
AC1
Attribute Check
24
3
read-write
AC2
Attribute Check
20
3
read-write
AC3
Attribute Check
16
3
read-write
AC4
Attribute Check
12
3
read-write
AC5
Attribute Check
8
3
read-write
AC6
Attribute Check
4
3
read-write
AC7
Attribute Check
0
3
read-write
RO0
Read Only
31
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO1
Read Only
27
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO2
Read Only
23
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO3
Read Only
19
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO4
Read Only
15
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO5
Read Only
11
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO6
Read Only
7
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO7
Read Only
3
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
PACRO
Peripheral Access Control Register
0x68
32
read-write
n
0x0
0x0
AC0
Attribute Check
28
3
read-write
AC1
Attribute Check
24
3
read-write
AC2
Attribute Check
20
3
read-write
AC3
Attribute Check
16
3
read-write
AC4
Attribute Check
12
3
read-write
AC5
Attribute Check
8
3
read-write
AC6
Attribute Check
4
3
read-write
AC7
Attribute Check
0
3
read-write
RO0
Read Only
31
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO1
Read Only
27
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO2
Read Only
23
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO3
Read Only
19
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO4
Read Only
15
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO5
Read Only
11
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO6
Read Only
7
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO7
Read Only
3
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
PACRP
Peripheral Access Control Register
0x6C
32
read-write
n
0x0
0x0
AC0
Attribute Check
28
3
read-write
AC1
Attribute Check
24
3
read-write
AC2
Attribute Check
20
3
read-write
AC3
Attribute Check
16
3
read-write
AC4
Attribute Check
12
3
read-write
AC5
Attribute Check
8
3
read-write
AC6
Attribute Check
4
3
read-write
AC7
Attribute Check
0
3
read-write
RO0
Read Only
31
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO1
Read Only
27
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO2
Read Only
23
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO3
Read Only
19
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO4
Read Only
15
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO5
Read Only
11
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO6
Read Only
7
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
RO7
Read Only
3
1
read-write
0
Writes to corresponding AC field are allowed.
#0
1
Writes to corresponding AC field are ignored.
#1
CMP0
High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
CMP
0x0
0x0
0x6
registers
n
CMP0_CMP1
14
CR0
CMP Control Register 0
0x0
8
read-write
n
0x0
0x0
FILTER_CNT
Filter Sample Count
4
3
read-write
000
Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
#000
001
One sample must agree. The comparator output is simply sampled.
#001
010
2 consecutive samples must agree.
#010
011
3 consecutive samples must agree.
#011
100
4 consecutive samples must agree.
#100
101
5 consecutive samples must agree.
#101
110
6 consecutive samples must agree.
#110
111
7 consecutive samples must agree.
#111
HYSTCTR
Comparator hard block hysteresis control
0
2
read-write
00
Level 0
#00
01
Level 1
#01
10
Level 2
#10
11
Level 3
#11
CR1
CMP Control Register 1
0x1
8
read-write
n
0x0
0x0
COS
Comparator Output Select
2
1
read-write
0
Set the filtered comparator output (CMPO) to equal COUT.
#0
1
Set the unfiltered comparator output (CMPO) to equal COUTA.
#1
EN
Comparator Module Enable
0
1
read-write
0
Analog Comparator is disabled.
#0
1
Analog Comparator is enabled.
#1
INV
Comparator INVERT
3
1
read-write
0
Does not invert the comparator output.
#0
1
Inverts the comparator output.
#1
OPE
Comparator Output Pin Enable
1
1
read-write
0
CMPO is not available on the associated CMPO output pin.
#0
1
CMPO is available on the associated CMPO output pin.
#1
PMODE
Power Mode Select
4
1
read-write
0
Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
#0
1
High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
#1
SE
Sample Enable
7
1
read-write
0
Sampling mode is not selected.
#0
1
Sampling mode is selected.
#1
TRIGM
Trigger Mode Enable
5
1
read-write
0
Trigger mode is disabled.
#0
1
Trigger mode is enabled.
#1
WE
Windowing Enable
6
1
read-write
0
Windowing mode is not selected.
#0
1
Windowing mode is selected.
#1
DACCR
DAC Control Register
0x4
8
read-write
n
0x0
0x0
DACEN
DAC Enable
7
1
read-write
0
DAC is disabled.
#0
1
DAC is enabled.
#1
VOSEL
DAC Output Voltage Select
0
6
read-write
VRSEL
Supply Voltage Reference Source Select
6
1
read-write
0
Vin1 is selected as resistor ladder network supply reference.
#0
1
Vin2 is selected as resistor ladder network supply reference.
#1
FPR
CMP Filter Period Register
0x2
8
read-write
n
0x0
0x0
FILT_PER
Filter Sample Period
0
8
read-write
MUXCR
MUX Control Register
0x5
8
read-write
n
0x0
0x0
MSEL
Minus Input Mux Control
0
3
read-write
000
IN0
#000
001
IN1
#001
010
IN2
#010
011
IN3
#011
100
IN4
#100
101
IN5
#101
110
IN6
#110
111
IN7
#111
PSEL
Plus Input Mux Control
3
3
read-write
000
IN0
#000
001
IN1
#001
010
IN2
#010
011
IN3
#011
100
IN4
#100
101
IN5
#101
110
IN6
#110
111
IN7
#111
SCR
CMP Status and Control Register
0x3
8
read-write
n
0x0
0x0
CFF
Analog Comparator Flag Falling
1
1
read-write
0
Falling-edge on COUT has not been detected.
#0
1
Falling-edge on COUT has occurred.
#1
CFR
Analog Comparator Flag Rising
2
1
read-write
0
Rising-edge on COUT has not been detected.
#0
1
Rising-edge on COUT has occurred.
#1
COUT
Analog Comparator Output
0
1
read-only
DMAEN
DMA Enable Control
6
1
read-write
0
DMA is disabled.
#0
1
DMA is enabled.
#1
IEF
Comparator Interrupt Enable Falling
3
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
IER
Comparator Interrupt Enable Rising
4
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
CMP1
High-Speed Comparator (CMP), Voltage Reference (VREF) Digital-to-Analog Converter (DAC), and Analog Mux (ANMUX)
CMP
0x0
0x0
0x6
registers
n
CMP0_CMP1
14
CR0
CMP Control Register 0
0x0
8
read-write
n
0x0
0x0
FILTER_CNT
Filter Sample Count
4
3
read-write
000
Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
#000
001
One sample must agree. The comparator output is simply sampled.
#001
010
2 consecutive samples must agree.
#010
011
3 consecutive samples must agree.
#011
100
4 consecutive samples must agree.
#100
101
5 consecutive samples must agree.
#101
110
6 consecutive samples must agree.
#110
111
7 consecutive samples must agree.
#111
HYSTCTR
Comparator hard block hysteresis control
0
2
read-write
00
Level 0
#00
01
Level 1
#01
10
Level 2
#10
11
Level 3
#11
CR1
CMP Control Register 1
0x1
8
read-write
n
0x0
0x0
COS
Comparator Output Select
2
1
read-write
0
Set the filtered comparator output (CMPO) to equal COUT.
#0
1
Set the unfiltered comparator output (CMPO) to equal COUTA.
#1
EN
Comparator Module Enable
0
1
read-write
0
Analog Comparator is disabled.
#0
1
Analog Comparator is enabled.
#1
INV
Comparator INVERT
3
1
read-write
0
Does not invert the comparator output.
#0
1
Inverts the comparator output.
#1
OPE
Comparator Output Pin Enable
1
1
read-write
0
CMPO is not available on the associated CMPO output pin.
#0
1
CMPO is available on the associated CMPO output pin.
#1
PMODE
Power Mode Select
4
1
read-write
0
Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
#0
1
High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
#1
SE
Sample Enable
7
1
read-write
0
Sampling mode is not selected.
#0
1
Sampling mode is selected.
#1
TRIGM
Trigger Mode Enable
5
1
read-write
0
Trigger mode is disabled.
#0
1
Trigger mode is enabled.
#1
WE
Windowing Enable
6
1
read-write
0
Windowing mode is not selected.
#0
1
Windowing mode is selected.
#1
DACCR
DAC Control Register
0x4
8
read-write
n
0x0
0x0
DACEN
DAC Enable
7
1
read-write
0
DAC is disabled.
#0
1
DAC is enabled.
#1
VOSEL
DAC Output Voltage Select
0
6
read-write
VRSEL
Supply Voltage Reference Source Select
6
1
read-write
0
Vin1 is selected as resistor ladder network supply reference.
#0
1
Vin2 is selected as resistor ladder network supply reference.
#1
FPR
CMP Filter Period Register
0x2
8
read-write
n
0x0
0x0
FILT_PER
Filter Sample Period
0
8
read-write
MUXCR
MUX Control Register
0x5
8
read-write
n
0x0
0x0
MSEL
Minus Input Mux Control
0
3
read-write
000
IN0
#000
001
IN1
#001
010
IN2
#010
011
IN3
#011
100
IN4
#100
101
IN5
#101
110
IN6
#110
111
IN7
#111
PSEL
Plus Input Mux Control
3
3
read-write
000
IN0
#000
001
IN1
#001
010
IN2
#010
011
IN3
#011
100
IN4
#100
101
IN5
#101
110
IN6
#110
111
IN7
#111
SCR
CMP Status and Control Register
0x3
8
read-write
n
0x0
0x0
CFF
Analog Comparator Flag Falling
1
1
read-write
0
Falling-edge on COUT has not been detected.
#0
1
Falling-edge on COUT has occurred.
#1
CFR
Analog Comparator Flag Rising
2
1
read-write
0
Rising-edge on COUT has not been detected.
#0
1
Rising-edge on COUT has occurred.
#1
COUT
Analog Comparator Output
0
1
read-only
DMAEN
DMA Enable Control
6
1
read-write
0
DMA is disabled.
#0
1
DMA is enabled.
#1
IEF
Comparator Interrupt Enable Falling
3
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
IER
Comparator Interrupt Enable Rising
4
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
CRC
Cyclic Redundancy Check
CRC
0x0
0x0
0xC
registers
n
CTRL
CRC Control register
0x8
32
read-write
n
0x0
0x0
FXOR
Complement Read Of CRC Data Register
26
1
read-write
0
No XOR on reading.
#0
1
Invert or complement the read value of the CRC Data register.
#1
TCRC
no description available
24
1
read-write
0
16-bit CRC protocol.
#0
1
32-bit CRC protocol.
#1
TOT
Type Of Transpose For Writes
30
2
read-write
00
No transposition.
#00
01
Bits in bytes are transposed; bytes are not transposed.
#01
10
Both bits in bytes and bytes are transposed.
#10
11
Only bytes are transposed; no bits in a byte are transposed.
#11
TOTR
Type Of Transpose For Read
28
2
read-write
00
No transposition.
#00
01
Bits in bytes are transposed; bytes are not transposed.
#01
10
Both bits in bytes and bytes are transposed.
#10
11
Only bytes are transposed; no bits in a byte are transposed.
#11
WAS
Write CRC Data Register As Seed
25
1
read-write
0
Writes to the CRC data register are data values.
#0
1
Writes to the CRC data register are seed values.
#1
CTRLHU
CRC_CTRLHU register.
0xB
8
read-write
n
0x0
0x0
FXOR
no description available
2
1
read-write
0
No XOR on reading.
#0
1
Invert or complement the read value of CRC data register.
#1
TCRC
no description available
0
1
read-write
0
16-bit CRC protocol.
#0
1
32-bit CRC protocol.
#1
TOT
no description available
6
2
read-write
00
No Transposition.
#00
01
Bits in bytes are transposed, bytes are not transposed.
#01
10
Both bits in bytes and bytes are transposed.
#10
11
Only bytes are transposed; no bits in a byte are transposed.
#11
TOTR
no description available
4
2
read-write
00
No Transposition.
#00
01
Bits in bytes are transposed, bytes are not transposed.
#01
10
Both bits in bytes and bytes are transposed.
#10
11
Only bytes are transposed; no bits in a byte are transposed.
#11
WAS
no description available
1
1
read-write
0
Writes to CRC data register are data values.
#0
1
Writes to CRC data reguster are seed values.
#1
DATA
CRC Data register
CRC
0x0
32
read-write
n
0x0
0x0
HL
CRC High Lower Byte
16
8
read-write
HU
CRC High Upper Byte
24
8
read-write
LL
CRC Low Lower Byte
0
8
read-write
LU
CRC Low Upper Byte
8
8
read-write
DATAH
CRC_DATAH register.
CRC
0x2
16
read-write
n
0x0
0x0
DATAH
DATAH stores the high 16 bits of the 16/32 bit CRC
0
16
read-write
DATAHL
CRC_DATAHL register.
CRC
0x2
8
read-write
n
0x0
0x0
DATAHL
DATAHL stores the third 8 bits of the 32 bit CRC
0
8
read-write
DATAHU
CRC_DATAHU register.
0x3
8
read-write
n
0x0
0x0
DATAHU
DATAHU stores the fourth 8 bits of the 32 bit CRC
0
8
read-write
DATAL
CRC_DATAL register.
CRC
0x0
16
read-write
n
0x0
0x0
DATAL
DATAL stores the lower 16 bits of the 16/32 bit CRC
0
16
read-write
DATALL
CRC_DATALL register.
CRC
0x0
8
read-write
n
0x0
0x0
DATALL
CRCLL stores the first 8 bits of the 32 bit DATA
0
8
read-write
DATALU
CRC_DATALU register.
0x1
8
read-write
n
0x0
0x0
DATALU
DATALL stores the second 8 bits of the 32 bit CRC
0
8
read-write
GPOLY
CRC Polynomial register
CRC
0x4
32
read-write
n
0x0
0x0
HIGH
High Polynominal Half-word
16
16
read-write
LOW
Low Polynominal Half-word
0
16
read-write
GPOLYH
CRC_GPOLYH register.
CRC
0x6
16
read-write
n
0x0
0x0
GPOLYH
POLYH stores the high 16 bits of the 16/32 bit CRC polynomial value
0
16
read-write
GPOLYHL
CRC_GPOLYHL register.
CRC
0x6
8
read-write
n
0x0
0x0
GPOLYHL
POLYHL stores the third 8 bits of the 32 bit CRC
0
8
read-write
GPOLYHU
CRC_GPOLYHU register.
0x7
8
read-write
n
0x0
0x0
GPOLYHU
POLYHU stores the fourth 8 bits of the 32 bit CRC
0
8
read-write
GPOLYL
CRC_GPOLYL register.
CRC
0x4
16
read-write
n
0x0
0x0
GPOLYL
POLYL stores the lower 16 bits of the 16/32 bit CRC polynomial value
0
16
read-write
GPOLYLL
CRC_GPOLYLL register.
CRC
0x4
8
read-write
n
0x0
0x0
GPOLYLL
POLYLL stores the first 8 bits of the 32 bit CRC
0
8
read-write
GPOLYLU
CRC_GPOLYLU register.
0x5
8
read-write
n
0x0
0x0
GPOLYLU
POLYLL stores the second 8 bits of the 32 bit CRC
0
8
read-write
DMA
DMA Controller
DMA
0x0
0x100
0x40
registers
n
DMA0
0
DMA1
1
DMA2
2
DMA3
3
DAR0
Destination Address Register
0x208
32
read-write
n
0x0
0x0
DAR
DAR
0
32
read-write
DAR1
Destination Address Register
0x31C
32
read-write
n
0x0
0x0
DAR
DAR
0
32
read-write
DAR2
Destination Address Register
0x440
32
read-write
n
0x0
0x0
DAR
DAR
0
32
read-write
DAR3
Destination Address Register
0x574
32
read-write
n
0x0
0x0
DAR
DAR
0
32
read-write
DCR0
DMA Control Register
0x218
32
read-write
n
0x0
0x0
AA
Auto-align
28
1
read-write
0
Auto-align disabled
#0
1
If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
#1
CHACR
Channel Access Control
26
2
read-write
CS
Cycle Steal
29
1
read-write
0
DMA continuously makes read/write transfers until the BCR decrements to 0.
#0
1
Forces a single read/write transfer per request.
#1
DINC
Destination Increment
19
1
read-write
0
No change to the DAR after a successful transfer.
#0
1
The DAR increments by 1, 2, 4 depending upon the size of the transfer.
#1
DMOD
Destination Address Modulo
8
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes
#0001
0010
Circular buffer size is 32 bytes
#0010
0011
Circular buffer size is 64 bytes
#0011
0100
Circular buffer size is 128 bytes
#0100
0101
Circular buffer size is 256 bytes
#0101
0110
Circular buffer size is 512 bytes
#0110
0111
Circular buffer size is 1 KB
#0111
1000
Circular buffer size is 2 KB
#1000
1001
Circular buffer size is 4 KB
#1001
1010
Circular buffer size is 8 KB
#1010
1011
Circular buffer size is 16 KB
#1011
1100
Circular buffer size is 32 KB
#1100
1101
Circular buffer size is 64 KB
#1101
1110
Circular buffer size is 128 KB
#1110
1111
Circular buffer size is 256 KB
#1111
DSIZE
Destination Size
17
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
D_REQ
Disable Request
7
1
read-write
0
ERQ bit is not affected.
#0
1
ERQ bit is cleared when the BCR is exhausted.
#1
EADREQ
Enable asynchronous DMA requests
23
1
read-write
0
Disabled
#0
1
Enabled
#1
EINT
Enable Interrupt on Completion of Transfer
31
1
read-write
0
No interrupt is generated.
#0
1
Interrupt signal is enabled.
#1
ERQ
Enable Peripheral Request
30
1
read-write
0
Peripheral request is ignored.
#0
1
Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.
#1
LCH1
Link Channel 1
2
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LCH2
Link Channel 2
0
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LINKCC
Link Channel Control
4
2
read-write
00
No channel-to-channel linking
#00
01
Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.
#01
10
Perform a link to channel LCH1 after each cycle-steal transfer
#10
11
Perform a link to channel LCH1 after the BCR decrements to 0.
#11
SINC
Source Increment
22
1
read-write
0
No change to SAR after a successful transfer.
#0
1
The SAR increments by 1, 2, 4 as determined by the transfer size.
#1
SMOD
Source Address Modulo
12
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes.
#0001
0010
Circular buffer size is 32 bytes.
#0010
0011
Circular buffer size is 64 bytes.
#0011
0100
Circular buffer size is 128 bytes.
#0100
0101
Circular buffer size is 256 bytes.
#0101
0110
Circular buffer size is 512 bytes.
#0110
0111
Circular buffer size is 1 KB.
#0111
1000
Circular buffer size is 2 KB.
#1000
1001
Circular buffer size is 4 KB.
#1001
1010
Circular buffer size is 8 KB.
#1010
1011
Circular buffer size is 16 KB.
#1011
1100
Circular buffer size is 32 KB.
#1100
1101
Circular buffer size is 64 KB.
#1101
1110
Circular buffer size is 128 KB.
#1110
1111
Circular buffer size is 256 KB.
#1111
SSIZE
Source Size
20
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
START
Start Transfer
16
1
write-only
0
DMA inactive
#0
1
The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
#1
UMNSM
User Mode, Nonsecure Mode
24
2
read-write
00
Channel attributes are set to the current mode.
#00
01
If the current mode is privileged and secure, then attributes are set to {privileged, secure}. Otherwise, writing this value terminates in an error.
#01
10
If the current mode is privileged and secure or if the current mode is user and secure, then attributes are set to {user, secure}. Otherwise, writing this value terminates in an error.
#10
11
If the current mode is privileged and secure, user and secure, or user and nonsecure, then attributes are set to {user, nonsecure}.
#11
DCR1
DMA Control Register
0x334
32
read-write
n
0x0
0x0
AA
Auto-align
28
1
read-write
0
Auto-align disabled
#0
1
If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
#1
CHACR
Channel Access Control
26
2
read-write
CS
Cycle Steal
29
1
read-write
0
DMA continuously makes read/write transfers until the BCR decrements to 0.
#0
1
Forces a single read/write transfer per request.
#1
DINC
Destination Increment
19
1
read-write
0
No change to the DAR after a successful transfer.
#0
1
The DAR increments by 1, 2, 4 depending upon the size of the transfer.
#1
DMOD
Destination Address Modulo
8
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes
#0001
0010
Circular buffer size is 32 bytes
#0010
0011
Circular buffer size is 64 bytes
#0011
0100
Circular buffer size is 128 bytes
#0100
0101
Circular buffer size is 256 bytes
#0101
0110
Circular buffer size is 512 bytes
#0110
0111
Circular buffer size is 1 KB
#0111
1000
Circular buffer size is 2 KB
#1000
1001
Circular buffer size is 4 KB
#1001
1010
Circular buffer size is 8 KB
#1010
1011
Circular buffer size is 16 KB
#1011
1100
Circular buffer size is 32 KB
#1100
1101
Circular buffer size is 64 KB
#1101
1110
Circular buffer size is 128 KB
#1110
1111
Circular buffer size is 256 KB
#1111
DSIZE
Destination Size
17
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
D_REQ
Disable Request
7
1
read-write
0
ERQ bit is not affected.
#0
1
ERQ bit is cleared when the BCR is exhausted.
#1
EADREQ
Enable asynchronous DMA requests
23
1
read-write
0
Disabled
#0
1
Enabled
#1
EINT
Enable Interrupt on Completion of Transfer
31
1
read-write
0
No interrupt is generated.
#0
1
Interrupt signal is enabled.
#1
ERQ
Enable Peripheral Request
30
1
read-write
0
Peripheral request is ignored.
#0
1
Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.
#1
LCH1
Link Channel 1
2
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LCH2
Link Channel 2
0
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LINKCC
Link Channel Control
4
2
read-write
00
No channel-to-channel linking
#00
01
Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.
#01
10
Perform a link to channel LCH1 after each cycle-steal transfer
#10
11
Perform a link to channel LCH1 after the BCR decrements to 0.
#11
SINC
Source Increment
22
1
read-write
0
No change to SAR after a successful transfer.
#0
1
The SAR increments by 1, 2, 4 as determined by the transfer size.
#1
SMOD
Source Address Modulo
12
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes.
#0001
0010
Circular buffer size is 32 bytes.
#0010
0011
Circular buffer size is 64 bytes.
#0011
0100
Circular buffer size is 128 bytes.
#0100
0101
Circular buffer size is 256 bytes.
#0101
0110
Circular buffer size is 512 bytes.
#0110
0111
Circular buffer size is 1 KB.
#0111
1000
Circular buffer size is 2 KB.
#1000
1001
Circular buffer size is 4 KB.
#1001
1010
Circular buffer size is 8 KB.
#1010
1011
Circular buffer size is 16 KB.
#1011
1100
Circular buffer size is 32 KB.
#1100
1101
Circular buffer size is 64 KB.
#1101
1110
Circular buffer size is 128 KB.
#1110
1111
Circular buffer size is 256 KB.
#1111
SSIZE
Source Size
20
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
START
Start Transfer
16
1
write-only
0
DMA inactive
#0
1
The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
#1
UMNSM
User Mode, Nonsecure Mode
24
2
read-write
00
Channel attributes are set to the current mode.
#00
01
If the current mode is privileged and secure, then attributes are set to {privileged, secure}. Otherwise, writing this value terminates in an error.
#01
10
If the current mode is privileged and secure or if the current mode is user and secure, then attributes are set to {user, secure}. Otherwise, writing this value terminates in an error.
#10
11
If the current mode is privileged and secure, user and secure, or user and nonsecure, then attributes are set to {user, nonsecure}.
#11
DCR2
DMA Control Register
0x460
32
read-write
n
0x0
0x0
AA
Auto-align
28
1
read-write
0
Auto-align disabled
#0
1
If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
#1
CHACR
Channel Access Control
26
2
read-write
CS
Cycle Steal
29
1
read-write
0
DMA continuously makes read/write transfers until the BCR decrements to 0.
#0
1
Forces a single read/write transfer per request.
#1
DINC
Destination Increment
19
1
read-write
0
No change to the DAR after a successful transfer.
#0
1
The DAR increments by 1, 2, 4 depending upon the size of the transfer.
#1
DMOD
Destination Address Modulo
8
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes
#0001
0010
Circular buffer size is 32 bytes
#0010
0011
Circular buffer size is 64 bytes
#0011
0100
Circular buffer size is 128 bytes
#0100
0101
Circular buffer size is 256 bytes
#0101
0110
Circular buffer size is 512 bytes
#0110
0111
Circular buffer size is 1 KB
#0111
1000
Circular buffer size is 2 KB
#1000
1001
Circular buffer size is 4 KB
#1001
1010
Circular buffer size is 8 KB
#1010
1011
Circular buffer size is 16 KB
#1011
1100
Circular buffer size is 32 KB
#1100
1101
Circular buffer size is 64 KB
#1101
1110
Circular buffer size is 128 KB
#1110
1111
Circular buffer size is 256 KB
#1111
DSIZE
Destination Size
17
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
D_REQ
Disable Request
7
1
read-write
0
ERQ bit is not affected.
#0
1
ERQ bit is cleared when the BCR is exhausted.
#1
EADREQ
Enable asynchronous DMA requests
23
1
read-write
0
Disabled
#0
1
Enabled
#1
EINT
Enable Interrupt on Completion of Transfer
31
1
read-write
0
No interrupt is generated.
#0
1
Interrupt signal is enabled.
#1
ERQ
Enable Peripheral Request
30
1
read-write
0
Peripheral request is ignored.
#0
1
Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.
#1
LCH1
Link Channel 1
2
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LCH2
Link Channel 2
0
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LINKCC
Link Channel Control
4
2
read-write
00
No channel-to-channel linking
#00
01
Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.
#01
10
Perform a link to channel LCH1 after each cycle-steal transfer
#10
11
Perform a link to channel LCH1 after the BCR decrements to 0.
#11
SINC
Source Increment
22
1
read-write
0
No change to SAR after a successful transfer.
#0
1
The SAR increments by 1, 2, 4 as determined by the transfer size.
#1
SMOD
Source Address Modulo
12
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes.
#0001
0010
Circular buffer size is 32 bytes.
#0010
0011
Circular buffer size is 64 bytes.
#0011
0100
Circular buffer size is 128 bytes.
#0100
0101
Circular buffer size is 256 bytes.
#0101
0110
Circular buffer size is 512 bytes.
#0110
0111
Circular buffer size is 1 KB.
#0111
1000
Circular buffer size is 2 KB.
#1000
1001
Circular buffer size is 4 KB.
#1001
1010
Circular buffer size is 8 KB.
#1010
1011
Circular buffer size is 16 KB.
#1011
1100
Circular buffer size is 32 KB.
#1100
1101
Circular buffer size is 64 KB.
#1101
1110
Circular buffer size is 128 KB.
#1110
1111
Circular buffer size is 256 KB.
#1111
SSIZE
Source Size
20
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
START
Start Transfer
16
1
write-only
0
DMA inactive
#0
1
The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
#1
UMNSM
User Mode, Nonsecure Mode
24
2
read-write
00
Channel attributes are set to the current mode.
#00
01
If the current mode is privileged and secure, then attributes are set to {privileged, secure}. Otherwise, writing this value terminates in an error.
#01
10
If the current mode is privileged and secure or if the current mode is user and secure, then attributes are set to {user, secure}. Otherwise, writing this value terminates in an error.
#10
11
If the current mode is privileged and secure, user and secure, or user and nonsecure, then attributes are set to {user, nonsecure}.
#11
DCR3
DMA Control Register
0x59C
32
read-write
n
0x0
0x0
AA
Auto-align
28
1
read-write
0
Auto-align disabled
#0
1
If SSIZE indicates a transfer no smaller than DSIZE, source accesses are auto-aligned; otherwise, destination accesses are auto-aligned. Source alignment takes precedence over destination alignment. If auto-alignment is enabled, the appropriate address register increments, regardless of DINC or SINC.
#1
CHACR
Channel Access Control
26
2
read-write
CS
Cycle Steal
29
1
read-write
0
DMA continuously makes read/write transfers until the BCR decrements to 0.
#0
1
Forces a single read/write transfer per request.
#1
DINC
Destination Increment
19
1
read-write
0
No change to the DAR after a successful transfer.
#0
1
The DAR increments by 1, 2, 4 depending upon the size of the transfer.
#1
DMOD
Destination Address Modulo
8
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes
#0001
0010
Circular buffer size is 32 bytes
#0010
0011
Circular buffer size is 64 bytes
#0011
0100
Circular buffer size is 128 bytes
#0100
0101
Circular buffer size is 256 bytes
#0101
0110
Circular buffer size is 512 bytes
#0110
0111
Circular buffer size is 1 KB
#0111
1000
Circular buffer size is 2 KB
#1000
1001
Circular buffer size is 4 KB
#1001
1010
Circular buffer size is 8 KB
#1010
1011
Circular buffer size is 16 KB
#1011
1100
Circular buffer size is 32 KB
#1100
1101
Circular buffer size is 64 KB
#1101
1110
Circular buffer size is 128 KB
#1110
1111
Circular buffer size is 256 KB
#1111
DSIZE
Destination Size
17
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
D_REQ
Disable Request
7
1
read-write
0
ERQ bit is not affected.
#0
1
ERQ bit is cleared when the BCR is exhausted.
#1
EADREQ
Enable asynchronous DMA requests
23
1
read-write
0
Disabled
#0
1
Enabled
#1
EINT
Enable Interrupt on Completion of Transfer
31
1
read-write
0
No interrupt is generated.
#0
1
Interrupt signal is enabled.
#1
ERQ
Enable Peripheral Request
30
1
read-write
0
Peripheral request is ignored.
#0
1
Enables peripheral request to initiate transfer. A software-initiated request (setting START) is always enabled.
#1
LCH1
Link Channel 1
2
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LCH2
Link Channel 2
0
2
read-write
00
DMA Channel 0
#00
01
DMA Channel 1
#01
10
DMA Channel 2
#10
11
DMA Channel 3
#11
LINKCC
Link Channel Control
4
2
read-write
00
No channel-to-channel linking
#00
01
Perform a link to channel LCH1 after each cycle-steal transfer followed by a link to LCH2 after the BCR decrements to 0.
#01
10
Perform a link to channel LCH1 after each cycle-steal transfer
#10
11
Perform a link to channel LCH1 after the BCR decrements to 0.
#11
SINC
Source Increment
22
1
read-write
0
No change to SAR after a successful transfer.
#0
1
The SAR increments by 1, 2, 4 as determined by the transfer size.
#1
SMOD
Source Address Modulo
12
4
read-write
0000
Buffer disabled
#0000
0001
Circular buffer size is 16 bytes.
#0001
0010
Circular buffer size is 32 bytes.
#0010
0011
Circular buffer size is 64 bytes.
#0011
0100
Circular buffer size is 128 bytes.
#0100
0101
Circular buffer size is 256 bytes.
#0101
0110
Circular buffer size is 512 bytes.
#0110
0111
Circular buffer size is 1 KB.
#0111
1000
Circular buffer size is 2 KB.
#1000
1001
Circular buffer size is 4 KB.
#1001
1010
Circular buffer size is 8 KB.
#1010
1011
Circular buffer size is 16 KB.
#1011
1100
Circular buffer size is 32 KB.
#1100
1101
Circular buffer size is 64 KB.
#1101
1110
Circular buffer size is 128 KB.
#1110
1111
Circular buffer size is 256 KB.
#1111
SSIZE
Source Size
20
2
read-write
00
32-bit
#00
01
8-bit
#01
10
16-bit
#10
11
Reserved (generates a configuration error (DSRn[CE]) if incorrectly specified at time of channel activation)
#11
START
Start Transfer
16
1
write-only
0
DMA inactive
#0
1
The DMA begins the transfer in accordance to the values in the TCDn. START is cleared automatically after one module clock and always reads as logic 0.
#1
UMNSM
User Mode, Nonsecure Mode
24
2
read-write
00
Channel attributes are set to the current mode.
#00
01
If the current mode is privileged and secure, then attributes are set to {privileged, secure}. Otherwise, writing this value terminates in an error.
#01
10
If the current mode is privileged and secure or if the current mode is user and secure, then attributes are set to {user, secure}. Otherwise, writing this value terminates in an error.
#10
11
If the current mode is privileged and secure, user and secure, or user and nonsecure, then attributes are set to {user, nonsecure}.
#11
DSR0
DMA_DSR0 register.
0x10B
8
read-write
n
0x0
0x0
DSR1
DMA_DSR1 register.
0x11B
8
read-write
n
0x0
0x0
DSR2
DMA_DSR2 register.
0x12B
8
read-write
n
0x0
0x0
DSR3
DMA_DSR3 register.
0x13B
8
read-write
n
0x0
0x0
DSR_BCR0
DMA Status Register / Byte Count Register
0x210
32
read-write
n
0x0
0x0
BCR
BCR
0
24
read-write
BED
Bus Error on Destination
28
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the write portion of a transfer.
#1
BES
Bus Error on Source
29
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the read portion of a transfer.
#1
BSY
Busy
25
1
read-only
0
DMA channel is inactive. Cleared when the DMA has finished the last transaction.
#0
1
BSY is set the first time the channel is enabled after a transfer is initiated.
#1
CE
Configuration Error
30
1
read-only
0
No configuration error exists.
#0
1
A configuration error has occurred.
#1
DONE
Transactions Done
24
1
read-write
0
DMA transfer is not yet complete. Writing a 0 has no effect.
#0
1
DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
#1
REQ
Request
26
1
read-only
0
No request is pending or the channel is currently active. Cleared when the channel is selected.
#0
1
The DMA channel has a transfer remaining and the channel is not selected.
#1
DSR_BCR1
DMA Status Register / Byte Count Register
0x328
32
read-write
n
0x0
0x0
BCR
BCR
0
24
read-write
BED
Bus Error on Destination
28
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the write portion of a transfer.
#1
BES
Bus Error on Source
29
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the read portion of a transfer.
#1
BSY
Busy
25
1
read-only
0
DMA channel is inactive. Cleared when the DMA has finished the last transaction.
#0
1
BSY is set the first time the channel is enabled after a transfer is initiated.
#1
CE
Configuration Error
30
1
read-only
0
No configuration error exists.
#0
1
A configuration error has occurred.
#1
DONE
Transactions Done
24
1
read-write
0
DMA transfer is not yet complete. Writing a 0 has no effect.
#0
1
DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
#1
REQ
Request
26
1
read-only
0
No request is pending or the channel is currently active. Cleared when the channel is selected.
#0
1
The DMA channel has a transfer remaining and the channel is not selected.
#1
DSR_BCR2
DMA Status Register / Byte Count Register
0x450
32
read-write
n
0x0
0x0
BCR
BCR
0
24
read-write
BED
Bus Error on Destination
28
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the write portion of a transfer.
#1
BES
Bus Error on Source
29
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the read portion of a transfer.
#1
BSY
Busy
25
1
read-only
0
DMA channel is inactive. Cleared when the DMA has finished the last transaction.
#0
1
BSY is set the first time the channel is enabled after a transfer is initiated.
#1
CE
Configuration Error
30
1
read-only
0
No configuration error exists.
#0
1
A configuration error has occurred.
#1
DONE
Transactions Done
24
1
read-write
0
DMA transfer is not yet complete. Writing a 0 has no effect.
#0
1
DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
#1
REQ
Request
26
1
read-only
0
No request is pending or the channel is currently active. Cleared when the channel is selected.
#0
1
The DMA channel has a transfer remaining and the channel is not selected.
#1
DSR_BCR3
DMA Status Register / Byte Count Register
0x588
32
read-write
n
0x0
0x0
BCR
BCR
0
24
read-write
BED
Bus Error on Destination
28
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the write portion of a transfer.
#1
BES
Bus Error on Source
29
1
read-only
0
No bus error occurred.
#0
1
The DMA channel terminated with a bus error during the read portion of a transfer.
#1
BSY
Busy
25
1
read-only
0
DMA channel is inactive. Cleared when the DMA has finished the last transaction.
#0
1
BSY is set the first time the channel is enabled after a transfer is initiated.
#1
CE
Configuration Error
30
1
read-only
0
No configuration error exists.
#0
1
A configuration error has occurred.
#1
DONE
Transactions Done
24
1
read-write
0
DMA transfer is not yet complete. Writing a 0 has no effect.
#0
1
DMA transfer completed. Writing a 1 to this bit clears all DMA status bits and should be used in an interrupt service routine to clear the DMA interrupt and error bits.
#1
REQ
Request
26
1
read-only
0
No request is pending or the channel is currently active. Cleared when the channel is selected.
#0
1
The DMA channel has a transfer remaining and the channel is not selected.
#1
SAR0
Source Address Register
0x200
32
read-write
n
0x0
0x0
SAR
SAR
0
32
read-write
SAR1
Source Address Register
0x310
32
read-write
n
0x0
0x0
SAR
SAR
0
32
read-write
SAR2
Source Address Register
0x430
32
read-write
n
0x0
0x0
SAR
SAR
0
32
read-write
SAR3
Source Address Register
0x560
32
read-write
n
0x0
0x0
SAR
SAR
0
32
read-write
DMAMUX0
DMA channel multiplexor
DMAMUX
0x0
0x0
0x1
registers
n
CHCFG
Channel Configuration register
0x0
8
read-write
n
0x0
0x0
ENBL
DMA Channel Enable
7
1
read-write
0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#0
1
DMA channel is enabled
#1
SOURCE
DMA Channel Source (Slot)
0
6
read-write
TRIG
DMA Channel Trigger Enable
6
1
read-write
0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#0
1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
#1
DMAMUX1
DMA channel multiplexor
DMAMUX
0x0
0x0
0x1
registers
n
CHCFG
Channel Configuration register
0x0
8
read-write
n
0x0
0x0
ENBL
DMA Channel Enable
7
1
read-write
0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#0
1
DMA channel is enabled
#1
SOURCE
DMA Channel Source (Slot)
0
6
read-write
TRIG
DMA Channel Trigger Enable
6
1
read-write
0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#0
1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
#1
DMAMUX2
DMA channel multiplexor
DMAMUX
0x0
0x0
0x1
registers
n
CHCFG
Channel Configuration register
0x0
8
read-write
n
0x0
0x0
ENBL
DMA Channel Enable
7
1
read-write
0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#0
1
DMA channel is enabled
#1
SOURCE
DMA Channel Source (Slot)
0
6
read-write
TRIG
DMA Channel Trigger Enable
6
1
read-write
0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#0
1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
#1
DMAMUX3
DMA channel multiplexor
DMAMUX
0x0
0x0
0x1
registers
n
CHCFG
Channel Configuration register
0x0
8
read-write
n
0x0
0x0
ENBL
DMA Channel Enable
7
1
read-write
0
DMA channel is disabled. This mode is primarily used during configuration of the DMAMux. The DMA has separate channel enables/disables, which should be used to disable or reconfigure a DMA channel.
#0
1
DMA channel is enabled
#1
SOURCE
DMA Channel Source (Slot)
0
6
read-write
TRIG
DMA Channel Trigger Enable
6
1
read-write
0
Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the specified source to the DMA channel. (Normal mode)
#0
1
Triggering is enabled. If triggering is enabled and ENBL is set, the DMAMUX is in Periodic Trigger mode.
#1
EWM
External Watchdog Monitor
EWM
0x0
0x0
0x4
registers
n
EWM
27
CMPH
Compare High Register
0x3
8
read-write
n
0x0
0x0
COMPAREH
no description available
0
8
read-write
CMPL
Compare Low Register
0x2
8
read-write
n
0x0
0x0
COMPAREL
no description available
0
8
read-write
CTRL
Control Register
0x0
8
read-write
n
0x0
0x0
ASSIN
EWM_in's Assertion State Select.
1
1
read-write
EWMEN
EWM enable.
0
1
read-write
INEN
Input Enable.
2
1
read-write
INTEN
Interrupt Enable.
3
1
read-write
SERV
Service Register
0x1
8
write-only
n
0x0
0x0
SERVICE
no description available
0
8
write-only
FTFA
Flash Memory Interface
FTFA
0x0
0x0
0x14
registers
n
FTFA
13
FCCOB0
Flash Common Command Object Registers
0x1A
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOB1
Flash Common Command Object Registers
0x13
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOB2
Flash Common Command Object Registers
0xD
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOB3
Flash Common Command Object Registers
0x8
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOB4
Flash Common Command Object Registers
0x40
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOB5
Flash Common Command Object Registers
0x35
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOB6
Flash Common Command Object Registers
0x2B
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOB7
Flash Common Command Object Registers
0x22
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOB8
Flash Common Command Object Registers
0x76
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOB9
Flash Common Command Object Registers
0x67
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOBA
Flash Common Command Object Registers
0x59
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCCOBB
Flash Common Command Object Registers
0x4C
8
read-write
n
0x0
0x0
CCOBn
no description available
0
8
read-write
FCNFG
Flash Configuration Register
0x1
8
read-write
n
0x0
0x0
CCIE
Command Complete Interrupt Enable
7
1
read-write
0
Command complete interrupt disabled
#0
1
Command complete interrupt enabled. An interrupt request is generated whenever the FSTAT[CCIF] flag is set.
#1
ERSAREQ
Erase All Request
5
1
read-only
0
No request or request complete
#0
1
Request to: run the Erase All Blocks command, verify the erased state, program the security byte in the Flash Configuration Field to the unsecure state, and release MCU security by setting the FSEC[SEC] field to the unsecure state.
#1
ERSSUSP
Erase Suspend
4
1
read-write
0
No suspend requested
#0
1
Suspend the current Erase Flash Sector command execution.
#1
RDCOLLIE
Read Collision Error Interrupt Enable
6
1
read-write
0
Read collision error interrupt disabled
#0
1
Read collision error interrupt enabled. An interrupt request is generated whenever a flash memory read collision error is detected (see the description of FSTAT[RDCOLERR]).
#1
FOPT
Flash Option Register
0x3
8
read-only
n
0x0
0x0
OPT
Nonvolatile Option
0
8
read-only
FPROT0
Program Flash Protection Registers
0x56
8
read-write
n
0x0
0x0
PROT
Program Flash Region Protect
0
8
read-write
0
Program flash region is protected.
#0
1
Program flash region is not protected
#1
FPROT1
Program Flash Protection Registers
0x43
8
read-write
n
0x0
0x0
PROT
Program Flash Region Protect
0
8
read-write
0
Program flash region is protected.
#0
1
Program flash region is not protected
#1
FPROT2
Program Flash Protection Registers
0x31
8
read-write
n
0x0
0x0
PROT
Program Flash Region Protect
0
8
read-write
0
Program flash region is protected.
#0
1
Program flash region is not protected
#1
FPROT3
Program Flash Protection Registers
0x20
8
read-write
n
0x0
0x0
PROT
Program Flash Region Protect
0
8
read-write
0
Program flash region is protected.
#0
1
Program flash region is not protected
#1
FSEC
Flash Security Register
0x2
8
read-only
n
0x0
0x0
FSLACC
Freescale Failure Analysis Access Code
2
2
read-only
00
Freescale factory access granted
#00
01
Freescale factory access denied
#01
10
Freescale factory access denied
#10
11
Freescale factory access granted
#11
KEYEN
Backdoor Key Security Enable
6
2
read-only
00
Backdoor key access disabled
#00
01
Backdoor key access disabled (preferred KEYEN state to disable backdoor key access)
#01
10
Backdoor key access enabled
#10
11
Backdoor key access disabled
#11
MEEN
Mass Erase Enable Bits
4
2
read-only
00
Mass erase is enabled
#00
01
Mass erase is enabled
#01
10
Mass erase is disabled
#10
11
Mass erase is enabled
#11
SEC
Flash Security
0
2
read-only
00
MCU security status is secure.
#00
01
MCU security status is secure.
#01
10
MCU security status is unsecure. (The standard shipping condition of the flash memory module is unsecure.)
#10
11
MCU security status is secure.
#11
FSTAT
Flash Status Register
0x0
8
read-write
n
0x0
0x0
ACCERR
Flash Access Error Flag
5
1
read-write
0
No access error detected
#0
1
Access error detected
#1
CCIF
Command Complete Interrupt Flag
7
1
read-write
0
Flash command in progress
#0
1
Flash command has completed
#1
FPVIOL
Flash Protection Violation Flag
4
1
read-write
0
No protection violation detected
#0
1
Protection violation detected
#1
MGSTAT0
Memory Controller Command Completion Status Flag
0
1
read-only
RDCOLERR
Flash Read Collision Error Flag
6
1
read-write
0
No collision error detected
#0
1
Collision error detected
#1
FTFA_FlashConfig
Flash configuration field
FTFA_FlashConfig
0x0
0x0
0xE
registers
n
BACKKEY0
Backdoor Comparison Key 0.
0x3
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY1
Backdoor Comparison Key 1.
0x2
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY2
Backdoor Comparison Key 2.
0x1
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY3
Backdoor Comparison Key 3.
0x0
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY4
Backdoor Comparison Key 4.
0x7
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY5
Backdoor Comparison Key 5.
0x6
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY6
Backdoor Comparison Key 6.
0x5
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
BACKKEY7
Backdoor Comparison Key 7.
0x4
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
FOPT
Non-volatile Flash Option Register
0xD
8
read-only
n
0x0
0x0
CLK_SRC
no description available
5
1
read-only
00
Externally supplied clock used by Flash
#00
01
Internal clock source used by Flash
#01
EXE_MODE
no description available
3
1
read-only
00
Execution Mode is RUN Mode
#00
01
Execution Mode is VLPR Mode
#01
LPBOOT
no description available
0
1
read-only
00
Low-power boot
#00
01
Normal boot
#01
NMI_EN
no description available
2
1
read-only
00
NMI interrupts are always blocked
#00
01
NMI_b pin/interrupts reset default to enabled
#01
FPROT0
Non-volatile P-Flash Protection 0 - High Register
0xB
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
FPROT1
Non-volatile P-Flash Protection 0 - Low Register
0xA
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
FPROT2
Non-volatile P-Flash Protection 1 - High Register
0x9
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
FPROT3
Non-volatile P-Flash Protection 1 - Low Register
0x8
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
FSEC
Non-volatile Flash Security Register
0xC
8
read-only
n
0x0
0x0
FSLACC
Freescale Failure Analysis Access Code
2
2
read-only
10
Freescale factory access denied
#10
11
Freescale factory access granted
#11
KEYEN
Backdoor Key Security Enable
6
2
read-only
10
Backdoor key access enabled
#10
11
Backdoor key access disabled
#11
MEEN
no description available
4
2
read-only
10
Mass erase is disabled
#10
11
Mass erase is enabled
#11
SEC
Flash Security
0
2
read-only
10
MCU security status is unsecure
#10
11
MCU security status is secure
#11
NV_BACKKEY0
Backdoor Comparison Key 0.
0x3
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY1
Backdoor Comparison Key 1.
0x2
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY2
Backdoor Comparison Key 2.
0x1
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY3
Backdoor Comparison Key 3.
0x0
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY4
Backdoor Comparison Key 4.
0x7
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY5
Backdoor Comparison Key 5.
0x6
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY6
Backdoor Comparison Key 6.
0x5
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_BACKKEY7
Backdoor Comparison Key 7.
0x4
8
read-only
n
0x0
0x0
KEY
Backdoor Comparison Key.
0
8
read-only
NV_FOPT
Non-volatile Flash Option Register
0xD
8
read-only
n
0x0
0x0
CLK_SRC
no description available
5
1
read-only
00
Externally supplied clock used by Flash
#00
01
Internal clock source used by Flash
#01
EXE_MODE
no description available
3
1
read-only
00
Execution Mode is RUN Mode
#00
01
Execution Mode is VLPR Mode
#01
LPBOOT
no description available
0
1
read-only
00
Low-power boot
#00
01
Normal boot
#01
NMI_EN
no description available
2
1
read-only
00
NMI interrupts are always blocked
#00
01
NMI_b pin/interrupts reset default to enabled
#01
NV_FPROT0
Non-volatile P-Flash Protection 0 - High Register
0xB
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
NV_FPROT1
Non-volatile P-Flash Protection 0 - Low Register
0xA
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
NV_FPROT2
Non-volatile P-Flash Protection 1 - High Register
0x9
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
NV_FPROT3
Non-volatile P-Flash Protection 1 - Low Register
0x8
8
read-only
n
0x0
0x0
PROT
P-Flash Region Protect
0
8
read-only
NV_FSEC
Non-volatile Flash Security Register
0xC
8
read-only
n
0x0
0x0
FSLACC
Freescale Failure Analysis Access Code
2
2
read-only
10
Freescale factory access denied
#10
11
Freescale factory access granted
#11
KEYEN
Backdoor Key Security Enable
6
2
read-only
10
Backdoor key access enabled
#10
11
Backdoor key access disabled
#11
MEEN
no description available
4
2
read-only
10
Mass erase is disabled
#10
11
Mass erase is enabled
#11
SEC
Flash Security
0
2
read-only
10
MCU security status is unsecure
#10
11
MCU security status is secure
#11
GPIOA
General Purpose Input/Output
GPIO
0x0
0x0
0x1D
registers
n
PTx
17
GACR
GPIO Attribute Checker Register
0x1C
8
read-write
n
0x0
0x0
ACB
Attribute Check Byte
0
3
read-write
000
User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write
#000
001
User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write
#001
010
User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write
#010
011
User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write
#011
100
User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write
#100
101
User nonsecure: None; User Secure: None; Privileged Secure: Read + Write
#101
110
User nonsecure: None; User Secure: None; Privileged Secure: Read
#110
111
User nonsecure: None; User Secure: None; Privileged Secure: None
#111
ROB
Read-Only Byte
7
1
read-write
0
Writes to the ACB are allowed.
#0
1
Writes to the ACB are ignored.
#1
PDDR
Port Data Direction Register
0x14
8
read-write
n
0x0
0x0
PDD
Port Data Direction
0
8
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
8
read-only
n
0x0
0x0
PDI
Port Data Input
0
8
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
8
read-write
n
0x0
0x0
PDO
Port Data Output
0
8
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
GPIOB
General Purpose Input/Output
GPIO
0x0
0x0
0x1D
registers
n
PTx
17
GACR
GPIO Attribute Checker Register
0x1C
8
read-write
n
0x0
0x0
ACB
Attribute Check Byte
0
3
read-write
000
User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write
#000
001
User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write
#001
010
User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write
#010
011
User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write
#011
100
User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write
#100
101
User nonsecure: None; User Secure: None; Privileged Secure: Read + Write
#101
110
User nonsecure: None; User Secure: None; Privileged Secure: Read
#110
111
User nonsecure: None; User Secure: None; Privileged Secure: None
#111
ROB
Read-Only Byte
7
1
read-write
0
Writes to the ACB are allowed.
#0
1
Writes to the ACB are ignored.
#1
PDDR
Port Data Direction Register
0x14
8
read-write
n
0x0
0x0
PDD
Port Data Direction
0
8
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
8
read-only
n
0x0
0x0
PDI
Port Data Input
0
8
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
8
read-write
n
0x0
0x0
PDO
Port Data Output
0
8
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
GPIOC
General Purpose Input/Output
GPIO
0x0
0x0
0x1D
registers
n
PTx
17
GACR
GPIO Attribute Checker Register
0x1C
8
read-write
n
0x0
0x0
ACB
Attribute Check Byte
0
3
read-write
000
User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write
#000
001
User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write
#001
010
User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write
#010
011
User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write
#011
100
User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write
#100
101
User nonsecure: None; User Secure: None; Privileged Secure: Read + Write
#101
110
User nonsecure: None; User Secure: None; Privileged Secure: Read
#110
111
User nonsecure: None; User Secure: None; Privileged Secure: None
#111
ROB
Read-Only Byte
7
1
read-write
0
Writes to the ACB are allowed.
#0
1
Writes to the ACB are ignored.
#1
PDDR
Port Data Direction Register
0x14
8
read-write
n
0x0
0x0
PDD
Port Data Direction
0
8
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
8
read-only
n
0x0
0x0
PDI
Port Data Input
0
8
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
8
read-write
n
0x0
0x0
PDO
Port Data Output
0
8
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
GPIOD
General Purpose Input/Output
GPIO
0x0
0x0
0x1D
registers
n
PTx
17
GACR
GPIO Attribute Checker Register
0x1C
8
read-write
n
0x0
0x0
ACB
Attribute Check Byte
0
3
read-write
000
User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write
#000
001
User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write
#001
010
User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write
#010
011
User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write
#011
100
User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write
#100
101
User nonsecure: None; User Secure: None; Privileged Secure: Read + Write
#101
110
User nonsecure: None; User Secure: None; Privileged Secure: Read
#110
111
User nonsecure: None; User Secure: None; Privileged Secure: None
#111
ROB
Read-Only Byte
7
1
read-write
0
Writes to the ACB are allowed.
#0
1
Writes to the ACB are ignored.
#1
PDDR
Port Data Direction Register
0x14
8
read-write
n
0x0
0x0
PDD
Port Data Direction
0
8
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
8
read-only
n
0x0
0x0
PDI
Port Data Input
0
8
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
8
read-write
n
0x0
0x0
PDO
Port Data Output
0
8
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
GPIOE
General Purpose Input/Output
GPIO
0x0
0x0
0x1D
registers
n
PTx
17
GACR
GPIO Attribute Checker Register
0x1C
8
read-write
n
0x0
0x0
ACB
Attribute Check Byte
0
3
read-write
000
User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write
#000
001
User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write
#001
010
User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write
#010
011
User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write
#011
100
User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write
#100
101
User nonsecure: None; User Secure: None; Privileged Secure: Read + Write
#101
110
User nonsecure: None; User Secure: None; Privileged Secure: Read
#110
111
User nonsecure: None; User Secure: None; Privileged Secure: None
#111
ROB
Read-Only Byte
7
1
read-write
0
Writes to the ACB are allowed.
#0
1
Writes to the ACB are ignored.
#1
PDDR
Port Data Direction Register
0x14
8
read-write
n
0x0
0x0
PDD
Port Data Direction
0
8
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
8
read-only
n
0x0
0x0
PDI
Port Data Input
0
8
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
8
read-write
n
0x0
0x0
PDO
Port Data Output
0
8
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
GPIOF
General Purpose Input/Output
GPIO
0x0
0x0
0x1D
registers
n
PTx
17
GACR
GPIO Attribute Checker Register
0x1C
8
read-write
n
0x0
0x0
ACB
Attribute Check Byte
0
3
read-write
000
User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write
#000
001
User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write
#001
010
User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write
#010
011
User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write
#011
100
User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write
#100
101
User nonsecure: None; User Secure: None; Privileged Secure: Read + Write
#101
110
User nonsecure: None; User Secure: None; Privileged Secure: Read
#110
111
User nonsecure: None; User Secure: None; Privileged Secure: None
#111
ROB
Read-Only Byte
7
1
read-write
0
Writes to the ACB are allowed.
#0
1
Writes to the ACB are ignored.
#1
PDDR
Port Data Direction Register
0x14
8
read-write
n
0x0
0x0
PDD
Port Data Direction
0
8
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
8
read-only
n
0x0
0x0
PDI
Port Data Input
0
8
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
8
read-write
n
0x0
0x0
PDO
Port Data Output
0
8
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
GPIOG
General Purpose Input/Output
GPIO
0x0
0x0
0x1D
registers
n
PTx
17
GACR
GPIO Attribute Checker Register
0x1C
8
read-write
n
0x0
0x0
ACB
Attribute Check Byte
0
3
read-write
000
User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write
#000
001
User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write
#001
010
User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write
#010
011
User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write
#011
100
User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write
#100
101
User nonsecure: None; User Secure: None; Privileged Secure: Read + Write
#101
110
User nonsecure: None; User Secure: None; Privileged Secure: Read
#110
111
User nonsecure: None; User Secure: None; Privileged Secure: None
#111
ROB
Read-Only Byte
7
1
read-write
0
Writes to the ACB are allowed.
#0
1
Writes to the ACB are ignored.
#1
PDDR
Port Data Direction Register
0x14
8
read-write
n
0x0
0x0
PDD
Port Data Direction
0
8
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
8
read-only
n
0x0
0x0
PDI
Port Data Input
0
8
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
8
read-write
n
0x0
0x0
PDO
Port Data Output
0
8
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
GPIOH
General Purpose Input/Output
GPIO
0x0
0x0
0x1D
registers
n
PTx
17
GACR
GPIO Attribute Checker Register
0x1C
8
read-write
n
0x0
0x0
ACB
Attribute Check Byte
0
3
read-write
000
User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write
#000
001
User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write
#001
010
User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write
#010
011
User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write
#011
100
User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write
#100
101
User nonsecure: None; User Secure: None; Privileged Secure: Read + Write
#101
110
User nonsecure: None; User Secure: None; Privileged Secure: Read
#110
111
User nonsecure: None; User Secure: None; Privileged Secure: None
#111
ROB
Read-Only Byte
7
1
read-write
0
Writes to the ACB are allowed.
#0
1
Writes to the ACB are ignored.
#1
PDDR
Port Data Direction Register
0x14
8
read-write
n
0x0
0x0
PDD
Port Data Direction
0
8
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
8
read-only
n
0x0
0x0
PDI
Port Data Input
0
8
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
8
read-write
n
0x0
0x0
PDO
Port Data Output
0
8
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
GPIOI
General Purpose Input/Output
GPIO
0x0
0x0
0x1D
registers
n
PTx
17
GACR
GPIO Attribute Checker Register
0x1C
8
read-write
n
0x0
0x0
ACB
Attribute Check Byte
0
3
read-write
000
User nonsecure: Read + Write; User Secure: Read + Write; Privileged Secure: Read + Write
#000
001
User nonsecure: Read; User Secure: Read + Write; Privileged Secure: Read + Write
#001
010
User nonsecure: None; User Secure: Read + Write; Privileged Secure: Read + Write
#010
011
User nonsecure: Read; User Secure: Read; Privileged Secure: Read + Write
#011
100
User nonsecure: None; User Secure: Read; Privileged Secure: Read + Write
#100
101
User nonsecure: None; User Secure: None; Privileged Secure: Read + Write
#101
110
User nonsecure: None; User Secure: None; Privileged Secure: Read
#110
111
User nonsecure: None; User Secure: None; Privileged Secure: None
#111
ROB
Read-Only Byte
7
1
read-write
0
Writes to the ACB are allowed.
#0
1
Writes to the ACB are ignored.
#1
PDDR
Port Data Direction Register
0x14
8
read-write
n
0x0
0x0
PDD
Port Data Direction
0
8
read-write
0
Pin is configured as general-purpose input, for the GPIO function.
#0
1
Pin is configured as general-purpose output, for the GPIO function.
#1
PDIR
Port Data Input Register
0x10
8
read-only
n
0x0
0x0
PDI
Port Data Input
0
8
read-only
0
Pin logic level is logic 0, or is not configured for use by digital function.
#0
1
Pin logic level is logic 1.
#1
PDOR
Port Data Output Register
0x0
8
read-write
n
0x0
0x0
PDO
Port Data Output
0
8
read-write
0
Logic level 0 is driven on pin, provided pin is configured for general-purpose output.
#0
1
Logic level 1 is driven on pin, provided pin is configured for general-purpose output.
#1
I2C0
Inter-Integrated Circuit
I2C
0x0
0x0
0xC
registers
n
I2C0_I2C1
26
A1
I2C Address Register 1
0x0
8
read-write
n
0x0
0x0
AD
Address
1
7
read-write
A2
I2C Address Register 2
0x9
8
read-write
n
0x0
0x0
SAD
SMBus Address
1
7
read-write
C1
I2C Control Register 1
0x2
8
read-write
n
0x0
0x0
DMAEN
DMA Enable
0
1
read-write
0
All DMA signalling disabled.
#0
1
DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.
#1
IICEN
I2C Enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
IICIE
I2C Interrupt Enable
6
1
read-write
0
Disabled
#0
1
Enabled
#1
MST
Master Mode Select
5
1
read-write
0
Slave mode
#0
1
Master mode
#1
RSTA
Repeat START
2
1
write-only
TX
Transmit Mode Select
4
1
read-write
0
Receive
#0
1
Transmit
#1
TXAK
Transmit Acknowledge Enable
3
1
read-write
0
An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
#0
1
No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
#1
WUEN
Wakeup Enable
1
1
read-write
0
Normal operation. No interrupt generated when address matching in low power mode.
#0
1
Enables the wakeup function in low power mode.
#1
C2
I2C Control Register 2
0x5
8
read-write
n
0x0
0x0
AD
Slave Address
0
3
read-write
ADEXT
Address Extension
6
1
read-write
0
7-bit address scheme
#0
1
10-bit address scheme
#1
GCAEN
General Call Address Enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
HDRS
High Drive Select
5
1
read-write
0
Normal drive mode
#0
1
High drive mode
#1
RMEN
Range Address Matching Enable
3
1
read-write
0
Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.
#0
1
Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
#1
SBRC
Slave Baud Rate Control
4
1
read-write
0
The slave baud rate follows the master baud rate and clock stretching may occur
#0
1
Slave baud rate is independent of the master baud rate
#1
D
I2C Data I/O register
0x4
8
read-write
n
0x0
0x0
DATA
Data
0
8
read-write
F
I2C Frequency Divider register
0x1
8
read-write
n
0x0
0x0
ICR
ClockRate
0
6
read-write
MULT
Multiplier Factor
6
2
read-write
00
mul = 1
#00
01
mul = 2
#01
10
mul = 4
#10
FLT
I2C Programmable Input Glitch Filter Register
0x6
8
read-write
n
0x0
0x0
FLT
I2C Programmable Filter Factor
0
4
read-write
0
No filter/bypass
#0
SHEN
Stop Hold Enable
7
1
read-write
0
Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
#0
1
Stop holdoff is enabled.
#1
SSIE
I2C Bus Stop or Start Interrupt Enable
5
1
read-write
0
Stop or start detection interrupt is disabled
#0
1
Stop or start detection interrupt is enabled
#1
STARTF
I2C Bus Start Detect Flag
4
1
read-write
0
No start happens on I2C bus
#0
1
Start detected on I2C bus
#1
STOPF
I2C Bus Stop Detect Flag
6
1
read-write
0
No stop happens on I2C bus
#0
1
Stop detected on I2C bus
#1
RA
I2C Range Address register
0x7
8
read-write
n
0x0
0x0
RAD
Range Slave Address
1
7
read-write
S
I2C Status register
0x3
8
read-write
n
0x0
0x0
ARBL
Arbitration Lost
4
1
read-write
0
Standard bus operation.
#0
1
Loss of arbitration.
#1
BUSY
Bus Busy
5
1
read-only
0
Bus is idle
#0
1
Bus is busy
#1
IAAS
Addressed As A Slave
6
1
read-write
0
Not addressed
#0
1
Addressed as a slave
#1
IICIF
Interrupt Flag
1
1
read-write
0
No interrupt pending
#0
1
Interrupt pending
#1
RAM
Range Address Match
3
1
read-write
0
Not addressed
#0
1
Addressed as a slave
#1
RXAK
Receive Acknowledge
0
1
read-only
0
Acknowledge signal was received after the completion of one byte of data transmission on the bus
#0
1
No acknowledge signal detected
#1
SRW
Slave Read/Write
2
1
read-only
0
Slave receive, master writing to slave
#0
1
Slave transmit, master reading from slave
#1
TCF
Transfer Complete Flag
7
1
read-only
0
Transfer in progress
#0
1
Transfer complete
#1
SLTH
I2C SCL Low Timeout Register High
0xA
8
read-write
n
0x0
0x0
SSLT
SSLT[15:8]
0
8
read-write
SLTL
I2C SCL Low Timeout Register Low
0xB
8
read-write
n
0x0
0x0
SSLT
SSLT[7:0]
0
8
read-write
SMB
I2C SMBus Control and Status register
0x8
8
read-write
n
0x0
0x0
ALERTEN
SMBus Alert Response Address Enable
6
1
read-write
0
SMBus alert response address matching is disabled
#0
1
SMBus alert response address matching is enabled
#1
FACK
Fast NACK/ACK Enable
7
1
read-write
0
An ACK or NACK is sent on the following receiving data byte
#0
1
Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
#1
SHTF1
SCL High Timeout Flag 1
2
1
read-only
0
No SCL high and SDA high timeout occurs
#0
1
SCL high and SDA high timeout occurs
#1
SHTF2
SCL High Timeout Flag 2
1
1
read-write
0
No SCL high and SDA low timeout occurs
#0
1
SCL high and SDA low timeout occurs
#1
SHTF2IE
SHTF2 Interrupt Enable
0
1
read-write
0
SHTF2 interrupt is disabled
#0
1
SHTF2 interrupt is enabled
#1
SIICAEN
Second I2C Address Enable
5
1
read-write
0
I2C address register 2 matching is disabled
#0
1
I2C address register 2 matching is enabled
#1
SLTF
SCL Low Timeout Flag
3
1
read-write
0
No low timeout occurs
#0
1
Low timeout occurs
#1
TCKSEL
Timeout Counter Clock Select
4
1
read-write
0
Timeout counter counts at the frequency of the I2C module clock / 64
#0
1
Timeout counter counts at the frequency of the I2C module clock
#1
I2C1
Inter-Integrated Circuit
I2C
0x0
0x0
0xC
registers
n
I2C0_I2C1
26
A1
I2C Address Register 1
0x0
8
read-write
n
0x0
0x0
AD
Address
1
7
read-write
A2
I2C Address Register 2
0x9
8
read-write
n
0x0
0x0
SAD
SMBus Address
1
7
read-write
C1
I2C Control Register 1
0x2
8
read-write
n
0x0
0x0
DMAEN
DMA Enable
0
1
read-write
0
All DMA signalling disabled.
#0
1
DMA transfer is enabled. While SMB[FACK] = 0, the following conditions trigger the DMA request: a data byte is received, and either address or data is transmitted. (ACK/NACK is automatic) the first byte received matches the A1 register or is a general call address. If any address matching occurs, S[IAAS] and S[TCF] are set. If the direction of transfer is known from master to slave, then it is not required to check S[SRW]. With this assumption, DMA can also be used in this case. In other cases, if the master reads data from the slave, then it is required to rewrite the C1 register operation. With this assumption, DMA cannot be used. When FACK = 1, an address or a data byte is transmitted.
#1
IICEN
I2C Enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
IICIE
I2C Interrupt Enable
6
1
read-write
0
Disabled
#0
1
Enabled
#1
MST
Master Mode Select
5
1
read-write
0
Slave mode
#0
1
Master mode
#1
RSTA
Repeat START
2
1
write-only
TX
Transmit Mode Select
4
1
read-write
0
Receive
#0
1
Transmit
#1
TXAK
Transmit Acknowledge Enable
3
1
read-write
0
An acknowledge signal is sent to the bus on the following receiving byte (if FACK is cleared) or the current receiving byte (if FACK is set).
#0
1
No acknowledge signal is sent to the bus on the following receiving data byte (if FACK is cleared) or the current receiving data byte (if FACK is set).
#1
WUEN
Wakeup Enable
1
1
read-write
0
Normal operation. No interrupt generated when address matching in low power mode.
#0
1
Enables the wakeup function in low power mode.
#1
C2
I2C Control Register 2
0x5
8
read-write
n
0x0
0x0
AD
Slave Address
0
3
read-write
ADEXT
Address Extension
6
1
read-write
0
7-bit address scheme
#0
1
10-bit address scheme
#1
GCAEN
General Call Address Enable
7
1
read-write
0
Disabled
#0
1
Enabled
#1
HDRS
High Drive Select
5
1
read-write
0
Normal drive mode
#0
1
High drive mode
#1
RMEN
Range Address Matching Enable
3
1
read-write
0
Range mode disabled. No address matching occurs for an address within the range of values of the A1 and RA registers.
#0
1
Range mode enabled. Address matching occurs when a slave receives an address within the range of values of the A1 and RA registers.
#1
SBRC
Slave Baud Rate Control
4
1
read-write
0
The slave baud rate follows the master baud rate and clock stretching may occur
#0
1
Slave baud rate is independent of the master baud rate
#1
D
I2C Data I/O register
0x4
8
read-write
n
0x0
0x0
DATA
Data
0
8
read-write
F
I2C Frequency Divider register
0x1
8
read-write
n
0x0
0x0
ICR
ClockRate
0
6
read-write
MULT
Multiplier Factor
6
2
read-write
00
mul = 1
#00
01
mul = 2
#01
10
mul = 4
#10
FLT
I2C Programmable Input Glitch Filter Register
0x6
8
read-write
n
0x0
0x0
FLT
I2C Programmable Filter Factor
0
4
read-write
0
No filter/bypass
#0
SHEN
Stop Hold Enable
7
1
read-write
0
Stop holdoff is disabled. The MCU's entry to stop mode is not gated.
#0
1
Stop holdoff is enabled.
#1
SSIE
I2C Bus Stop or Start Interrupt Enable
5
1
read-write
0
Stop or start detection interrupt is disabled
#0
1
Stop or start detection interrupt is enabled
#1
STARTF
I2C Bus Start Detect Flag
4
1
read-write
0
No start happens on I2C bus
#0
1
Start detected on I2C bus
#1
STOPF
I2C Bus Stop Detect Flag
6
1
read-write
0
No stop happens on I2C bus
#0
1
Stop detected on I2C bus
#1
RA
I2C Range Address register
0x7
8
read-write
n
0x0
0x0
RAD
Range Slave Address
1
7
read-write
S
I2C Status register
0x3
8
read-write
n
0x0
0x0
ARBL
Arbitration Lost
4
1
read-write
0
Standard bus operation.
#0
1
Loss of arbitration.
#1
BUSY
Bus Busy
5
1
read-only
0
Bus is idle
#0
1
Bus is busy
#1
IAAS
Addressed As A Slave
6
1
read-write
0
Not addressed
#0
1
Addressed as a slave
#1
IICIF
Interrupt Flag
1
1
read-write
0
No interrupt pending
#0
1
Interrupt pending
#1
RAM
Range Address Match
3
1
read-write
0
Not addressed
#0
1
Addressed as a slave
#1
RXAK
Receive Acknowledge
0
1
read-only
0
Acknowledge signal was received after the completion of one byte of data transmission on the bus
#0
1
No acknowledge signal detected
#1
SRW
Slave Read/Write
2
1
read-only
0
Slave receive, master writing to slave
#0
1
Slave transmit, master reading from slave
#1
TCF
Transfer Complete Flag
7
1
read-only
0
Transfer in progress
#0
1
Transfer complete
#1
SLTH
I2C SCL Low Timeout Register High
0xA
8
read-write
n
0x0
0x0
SSLT
SSLT[15:8]
0
8
read-write
SLTL
I2C SCL Low Timeout Register Low
0xB
8
read-write
n
0x0
0x0
SSLT
SSLT[7:0]
0
8
read-write
SMB
I2C SMBus Control and Status register
0x8
8
read-write
n
0x0
0x0
ALERTEN
SMBus Alert Response Address Enable
6
1
read-write
0
SMBus alert response address matching is disabled
#0
1
SMBus alert response address matching is enabled
#1
FACK
Fast NACK/ACK Enable
7
1
read-write
0
An ACK or NACK is sent on the following receiving data byte
#0
1
Writing 0 to TXAK after receiving a data byte generates an ACK. Writing 1 to TXAK after receiving a data byte generates a NACK.
#1
SHTF1
SCL High Timeout Flag 1
2
1
read-only
0
No SCL high and SDA high timeout occurs
#0
1
SCL high and SDA high timeout occurs
#1
SHTF2
SCL High Timeout Flag 2
1
1
read-write
0
No SCL high and SDA low timeout occurs
#0
1
SCL high and SDA low timeout occurs
#1
SHTF2IE
SHTF2 Interrupt Enable
0
1
read-write
0
SHTF2 interrupt is disabled
#0
1
SHTF2 interrupt is enabled
#1
SIICAEN
Second I2C Address Enable
5
1
read-write
0
I2C address register 2 matching is disabled
#0
1
I2C address register 2 matching is enabled
#1
SLTF
SCL Low Timeout Flag
3
1
read-write
0
No low timeout occurs
#0
1
Low timeout occurs
#1
TCKSEL
Timeout Counter Clock Select
4
1
read-write
0
Timeout counter counts at the frequency of the I2C module clock / 64
#0
1
Timeout counter counts at the frequency of the I2C module clock
#1
LCD
Segment Liquid Crystal Display
LCD
0x0
0x0
0x60
registers
n
LCD
15
AR
LCD Auxiliary Register
0x4
32
read-write
n
0x0
0x0
ALT
Alternate display mode
6
1
read-write
0
Normal display mode.
#0
1
Alternate display mode.
#1
BLANK
Blank display mode
5
1
read-write
0
Normal or alternate display mode.
#0
1
Blank display mode.
#1
BLINK
Blink command
7
1
read-write
0
Disables blinking.
#0
1
Starts blinking at blinking frequency specified by LCD blink rate calculation.
#1
BMODE
Blink mode
3
1
read-write
0
Display blank during the blink period.
#0
1
Display alternate display during blink period (Ignored if duty is 5 or greater).
#1
BRATE
Blink-rate configuration
0
3
read-write
LCDIF
LCD Frame Frequency Interrupt flag
15
1
read-write
0
Frame frequency interrupt condition has not occurred.
#0
1
Start of SLCD frame has occurred.
#1
BPENH
LCD Back Plane Enable register
0x4C
32
read-write
n
0x0
0x0
BPEN
Back Plane Enable
0
32
read-write
0
Front plane operation enabled on LCD_Pn.
#0
1
Back plane operation enabled on LCD_Pn.
#1
BPENL
LCD Back Plane Enable register
0x30
32
read-write
n
0x0
0x0
BPEN
Back Plane Enable
0
32
read-write
0
Front plane operation enabled on LCD_Pn.
#0
1
Back plane operation enabled on LCD_Pn.
#1
FDCR
LCD Fault Detect Control Register
0x8
32
read-write
n
0x0
0x0
FDBPEN
Fault Detect Back Plane Enable
6
1
read-write
0
Type of the selected pin under fault detect test is front plane.
#0
1
Type of the selected pin under fault detect test is back plane.
#1
FDEN
Fault Detect Enable
7
1
read-write
0
Disable fault detection.
#0
1
Enable fault detection.
#1
FDPINID
Fault Detect Pin ID
0
6
read-write
0
Fault detection for LCD_P0 pin.
#0
1
Fault detection for LCD_P1 pin.
#1
FDPRS
Fault Detect Clock Prescaler
12
3
read-write
0
1/1 bus clock.
#0
1
1/2 bus clock.
#1
FDSWW
Fault Detect Sample Window Width
9
3
read-write
0
Sample window width is 4 sample clock cycles.
#0
1
Sample window width is 8 sample clock cycles.
#1
FDSR
LCD Fault Detect Status Register
0xC
32
read-write
n
0x0
0x0
FDCF
Fault Detection Complete Flag
15
1
read-write
0
Fault detection is not completed.
#0
1
Fault detection is completed.
#1
FDCNT
Fault Detect Counter
0
8
read-only
0
No "one" samples.
#0
1
1 "one" samples.
#1
GCR
LCD General Control Register
0x0
32
read-write
n
0x0
0x0
ALTDIV
LCD AlternateClock Divider
12
2
read-write
0
Divide factor = 1 (No divide)
#0
1
Divide factor = 8
#1
CPSEL
Charge Pump or Resistor Bias Select
23
1
read-write
0
LCD charge pump is disabled. Resistor network selected. (The internal 1/3-bias is forced.)
#0
1
LCD charge pump is selected. Resistor network disabled. (The internal 1/3-bias is forced.)
#1
DUTY
LCD duty select
0
3
read-write
000
Use 1 BP (1/1 duty cycle).
#000
001
Use 2 BP (1/2 duty cycle).
#001
010
Use 3 BP (1/3 duty cycle).
#010
011
Use 4 BP (1/4 duty cycle). (Default)
#011
100
Use 5 BP (1/5 duty cycle).
#100
101
Use 6 BP (1/6 duty cycle).
#101
110
Use 7 BP (1/7 duty cycle).
#110
111
Use 8 BP (1/8 duty cycle).
#111
FDCIEN
LCD Fault Detection Complete Interrupt Enable
14
1
read-write
0
No interrupt request is generated by this event.
#0
1
When a fault is detected and FDCF bit is set, this event causes an interrupt request.
#1
LADJ
Load Adjust
20
2
read-write
LCDDOZE
LCD Doze enable
9
1
read-write
0
Allows the LCD driver, charge pump, resistor bias network, and voltage regulator to continue running during Doze mode.
#0
1
Disables the LCD driver, charge pump, resistor bias network, and voltage regulator when MCU enters Doze mode.
#1
LCDEN
LCD Driver Enable
7
1
read-write
0
All front plane and back plane pins are disabled. The LCD controller system is also disabled, and all LCD waveform generation clocks are stopped. V LL3 is connected to V DD internally.
#0
1
LCD controller driver system is enabled, and front plane and back plane waveforms are generated. All LCD pins, LCD_Pn, enabled using the LCD Pin Enable register, output an LCD driver waveform. The back plane pins output an LCD driver back plane waveform based on the settings of DUTY[2:0]. Charge pump or resistor bias is enabled.
#1
LCDIEN
LCD Frame Frequency Interrupt Enable
15
1
read-write
0
No interrupt request is generated by this event.
#0
1
When LCDIF bit is set, this event causes an interrupt request.
#1
LCDSTP
LCD Stop
8
1
read-write
0
Allows the LCD driver, charge pump, resistor bias network, and voltage regulator to continue running during Stop mode.
#0
1
Disables the LCD driver, charge pump, resistor bias network, and voltage regulator when MCU enters Stop mode.
#1
LCLK
LCD Clock Prescaler
3
3
read-write
RVEN
Regulated Voltage Enable
31
1
read-write
0
Regulated voltage disabled.
#0
1
Regulated voltage enabled.
#1
RVTRIM
Regulated Voltage Trim
24
4
read-write
SOURCE
LCD Clock Source Select
6
1
read-write
0
Selects the default clock as the LCD clock source.
#0
1
Selects the alternate clock as the LCD clock source.
#1
VSUPPLY
Voltage Supply Control
17
1
read-write
0
Drive VLL3 internally from VDD
#0
1
Drive VLL3 externally from VDD or drive VLL internally from vIREG
#1
PENH
LCD Pin Enable register
0x34
32
read-write
n
0x0
0x0
PEN
LCD Pin Enable
0
32
read-write
0
LCD operation disabled on LCD_Pn.
#0
1
LCD operation enabled on LCD_Pn.
#1
PENL
LCD Pin Enable register
0x20
32
read-write
n
0x0
0x0
PEN
LCD Pin Enable
0
32
read-write
0
LCD operation disabled on LCD_Pn.
#0
1
LCD operation enabled on LCD_Pn.
#1
WF0
LCD Waveform Register 0.
LCD
0x20
8
read-write
n
0x0
0x0
BPALCD0
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD0
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD0
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD0
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD0
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD0
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD0
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD0
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF1
LCD Waveform Register 1.
0x21
8
read-write
n
0x0
0x0
BPALCD1
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD1
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD1
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD1
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD1
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD1
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD1
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD1
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF10
LCD Waveform Register 10.
0x2A
8
read-write
n
0x0
0x0
BPALCD10
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD10
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD10
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD10
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD10
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD10
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD10
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD10
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF11
LCD Waveform Register 11.
0x2B
8
read-write
n
0x0
0x0
BPALCD11
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD11
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD11
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD11
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD11
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD11
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD11
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD11
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF11TO8
LCD Waveform register
LCD
0x28
32
read-write
n
0x0
0x0
WF10
no description available
16
8
read-write
WF11
no description available
24
8
read-write
WF8
no description available
0
8
read-write
WF9
no description available
8
8
read-write
WF12
LCD Waveform Register 12.
LCD
0x2C
8
read-write
n
0x0
0x0
BPALCD12
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD12
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD12
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD12
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD12
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD12
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD12
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD12
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF13
LCD Waveform Register 13.
0x2D
8
read-write
n
0x0
0x0
BPALCD13
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD13
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD13
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD13
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD13
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD13
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD13
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD13
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF14
LCD Waveform Register 14.
0x2E
8
read-write
n
0x0
0x0
BPALCD14
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD14
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD14
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD14
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD14
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD14
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD14
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD14
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF15
LCD Waveform Register 15.
0x2F
8
read-write
n
0x0
0x0
BPALCD15
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD15
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD15
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD15
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD15
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD15
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD15
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD15
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF15TO12
LCD Waveform register
LCD
0x2C
32
read-write
n
0x0
0x0
WF12
no description available
0
8
read-write
WF13
no description available
8
8
read-write
WF14
no description available
16
8
read-write
WF15
no description available
24
8
read-write
WF16
LCD Waveform Register 16.
LCD
0x30
8
read-write
n
0x0
0x0
BPALCD16
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD16
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD16
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD16
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD16
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD16
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD16
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD16
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF17
LCD Waveform Register 17.
0x31
8
read-write
n
0x0
0x0
BPALCD17
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD17
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD17
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD17
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD17
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD17
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD17
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD17
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF18
LCD Waveform Register 18.
0x32
8
read-write
n
0x0
0x0
BPALCD18
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD18
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD18
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD18
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD18
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD18
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD18
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD18
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF19
LCD Waveform Register 19.
0x33
8
read-write
n
0x0
0x0
BPALCD19
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD19
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD19
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD19
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD19
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD19
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD19
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD19
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF19TO16
LCD Waveform register
LCD
0x30
32
read-write
n
0x0
0x0
WF16
no description available
0
8
read-write
WF17
no description available
8
8
read-write
WF18
no description available
16
8
read-write
WF19
no description available
24
8
read-write
WF2
LCD Waveform Register 2.
0x22
8
read-write
n
0x0
0x0
BPALCD2
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD2
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD2
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD2
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD2
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD2
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD2
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD2
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF20
LCD Waveform Register 20.
LCD
0x34
8
read-write
n
0x0
0x0
BPALCD20
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD20
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD20
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD20
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD20
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD20
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD20
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD20
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF21
LCD Waveform Register 21.
0x35
8
read-write
n
0x0
0x0
BPALCD21
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD21
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD21
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD21
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD21
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD21
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD21
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD21
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF22
LCD Waveform Register 22.
0x36
8
read-write
n
0x0
0x0
BPALCD22
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD22
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD22
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD22
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD22
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD22
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD22
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD22
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF23
LCD Waveform Register 23.
0x37
8
read-write
n
0x0
0x0
BPALCD23
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD23
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD23
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD23
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD23
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD23
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD23
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD23
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF23TO20
LCD Waveform register
LCD
0x34
32
read-write
n
0x0
0x0
WF20
no description available
0
8
read-write
WF21
no description available
8
8
read-write
WF22
no description available
16
8
read-write
WF23
no description available
24
8
read-write
WF24
LCD Waveform Register 24.
LCD
0x38
8
read-write
n
0x0
0x0
BPALCD24
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD24
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD24
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD24
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD24
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD24
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD24
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD24
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF25
LCD Waveform Register 25.
0x39
8
read-write
n
0x0
0x0
BPALCD25
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD25
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD25
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD25
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD25
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD25
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD25
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD25
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF26
LCD Waveform Register 26.
0x3A
8
read-write
n
0x0
0x0
BPALCD26
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD26
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD26
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD26
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD26
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD26
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD26
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD26
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF27
LCD Waveform Register 27.
0x3B
8
read-write
n
0x0
0x0
BPALCD27
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD27
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD27
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD27
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD27
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD27
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD27
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD27
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF27TO24
LCD Waveform register
LCD
0x38
32
read-write
n
0x0
0x0
WF24
no description available
0
8
read-write
WF25
no description available
8
8
read-write
WF26
no description available
16
8
read-write
WF27
no description available
24
8
read-write
WF28
LCD Waveform Register 28.
LCD
0x3C
8
read-write
n
0x0
0x0
BPALCD28
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD28
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD28
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD28
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD28
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD28
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD28
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD28
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF29
LCD Waveform Register 29.
0x3D
8
read-write
n
0x0
0x0
BPALCD29
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD29
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD29
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD29
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD29
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD29
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD29
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD29
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF3
LCD Waveform Register 3.
0x23
8
read-write
n
0x0
0x0
BPALCD3
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD3
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD3
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD3
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD3
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD3
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD3
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD3
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF30
LCD Waveform Register 30.
0x3E
8
read-write
n
0x0
0x0
BPALCD30
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD30
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD30
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD30
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD30
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD30
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD30
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD30
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF31
LCD Waveform Register 31.
0x3F
8
read-write
n
0x0
0x0
BPALCD31
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD31
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD31
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD31
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD31
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD31
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD31
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD31
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF31TO28
LCD Waveform register
LCD
0x3C
32
read-write
n
0x0
0x0
WF28
no description available
0
8
read-write
WF29
no description available
8
8
read-write
WF30
no description available
16
8
read-write
WF31
no description available
24
8
read-write
WF32
LCD Waveform Register 32.
LCD
0x40
8
read-write
n
0x0
0x0
BPALCD32
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD32
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD32
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD32
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD32
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD32
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD32
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD32
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF33
LCD Waveform Register 33.
0x41
8
read-write
n
0x0
0x0
BPALCD33
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD33
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD33
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD33
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD33
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD33
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD33
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD33
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF34
LCD Waveform Register 34.
0x42
8
read-write
n
0x0
0x0
BPALCD34
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD34
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD34
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD34
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD34
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD34
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD34
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD34
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF35
LCD Waveform Register 35.
0x43
8
read-write
n
0x0
0x0
BPALCD35
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD35
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD35
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD35
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD35
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD35
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD35
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD35
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF35TO32
LCD Waveform register
LCD
0x40
32
read-write
n
0x0
0x0
WF32
no description available
0
8
read-write
WF33
no description available
8
8
read-write
WF34
no description available
16
8
read-write
WF35
no description available
24
8
read-write
WF36
LCD Waveform Register 36.
LCD
0x44
8
read-write
n
0x0
0x0
BPALCD36
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD36
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD36
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD36
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD36
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD36
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD36
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD36
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF37
LCD Waveform Register 37.
0x45
8
read-write
n
0x0
0x0
BPALCD37
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD37
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD37
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD37
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD37
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD37
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD37
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD37
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF38
LCD Waveform Register 38.
0x46
8
read-write
n
0x0
0x0
BPALCD38
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD38
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD38
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD38
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD38
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD38
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD38
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD38
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF39
LCD Waveform Register 39.
0x47
8
read-write
n
0x0
0x0
BPALCD39
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD39
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD39
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD39
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD39
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD39
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD39
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD39
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF39TO36
LCD Waveform register
LCD
0x44
32
read-write
n
0x0
0x0
WF36
no description available
0
8
read-write
WF37
no description available
8
8
read-write
WF38
no description available
16
8
read-write
WF39
no description available
24
8
read-write
WF3TO0
LCD Waveform register
LCD
0x20
32
read-write
n
0x0
0x0
WF0
no description available
0
8
read-write
WF1
no description available
8
8
read-write
WF2
no description available
16
8
read-write
WF3
no description available
24
8
read-write
WF4
LCD Waveform Register 4.
LCD
0x24
8
read-write
n
0x0
0x0
BPALCD4
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD4
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD4
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD4
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD4
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD4
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD4
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD4
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF40
LCD Waveform Register 40.
LCD
0x48
8
read-write
n
0x0
0x0
BPALCD40
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD40
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD40
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD40
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD40
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD40
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD40
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD40
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF41
LCD Waveform Register 41.
0x49
8
read-write
n
0x0
0x0
BPALCD41
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD41
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD41
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD41
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD41
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD41
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD41
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD41
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF42
LCD Waveform Register 42.
0x4A
8
read-write
n
0x0
0x0
BPALCD42
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD42
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD42
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD42
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD42
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD42
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD42
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD42
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF43
LCD Waveform Register 43.
0x4B
8
read-write
n
0x0
0x0
BPALCD43
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD43
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD43
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD43
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD43
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD43
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD43
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD43
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF43TO40
LCD Waveform register
LCD
0x48
32
read-write
n
0x0
0x0
WF40
no description available
0
8
read-write
WF41
no description available
8
8
read-write
WF42
no description available
16
8
read-write
WF43
no description available
24
8
read-write
WF44
LCD Waveform Register 44.
LCD
0x4C
8
read-write
n
0x0
0x0
BPALCD44
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD44
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD44
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD44
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD44
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD44
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD44
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD44
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF45
LCD Waveform Register 45.
0x4D
8
read-write
n
0x0
0x0
BPALCD45
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD45
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD45
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD45
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD45
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD45
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD45
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD45
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF46
LCD Waveform Register 46.
0x4E
8
read-write
n
0x0
0x0
BPALCD46
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD46
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD46
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD46
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD46
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD46
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD46
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD46
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF47
LCD Waveform Register 47.
0x4F
8
read-write
n
0x0
0x0
BPALCD47
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD47
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD47
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD47
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD47
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD47
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD47
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD47
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF47TO44
LCD Waveform register
LCD
0x4C
32
read-write
n
0x0
0x0
WF44
no description available
0
8
read-write
WF45
no description available
8
8
read-write
WF46
no description available
16
8
read-write
WF47
no description available
24
8
read-write
WF48
LCD Waveform Register 48.
LCD
0x50
8
read-write
n
0x0
0x0
BPALCD48
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD48
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD48
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD48
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD48
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD48
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD48
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD48
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF49
LCD Waveform Register 49.
0x51
8
read-write
n
0x0
0x0
BPALCD49
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD49
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD49
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD49
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD49
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD49
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD49
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD49
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF5
LCD Waveform Register 5.
0x25
8
read-write
n
0x0
0x0
BPALCD5
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD5
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD5
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD5
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD5
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD5
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD5
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD5
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF50
LCD Waveform Register 50.
0x52
8
read-write
n
0x0
0x0
BPALCD50
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD50
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD50
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD50
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD50
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD50
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD50
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD50
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF51
LCD Waveform Register 51.
0x53
8
read-write
n
0x0
0x0
BPALCD51
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD51
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD51
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD51
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD51
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD51
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD51
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD51
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF51TO48
LCD Waveform register
LCD
0x50
32
read-write
n
0x0
0x0
WF48
no description available
0
8
read-write
WF49
no description available
8
8
read-write
WF50
no description available
16
8
read-write
WF51
no description available
24
8
read-write
WF52
LCD Waveform Register 52.
LCD
0x54
8
read-write
n
0x0
0x0
BPALCD52
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD52
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD52
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD52
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD52
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD52
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD52
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD52
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF53
LCD Waveform Register 53.
0x55
8
read-write
n
0x0
0x0
BPALCD53
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD53
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD53
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD53
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD53
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD53
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD53
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD53
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF54
LCD Waveform Register 54.
0x56
8
read-write
n
0x0
0x0
BPALCD54
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD54
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD54
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD54
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD54
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD54
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD54
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD54
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF55
LCD Waveform Register 55.
0x57
8
read-write
n
0x0
0x0
BPALCD55
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD55
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD55
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD55
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD55
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD55
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD55
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD55
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF55TO52
LCD Waveform register
LCD
0x54
32
read-write
n
0x0
0x0
WF52
no description available
0
8
read-write
WF53
no description available
8
8
read-write
WF54
no description available
16
8
read-write
WF55
no description available
24
8
read-write
WF56
LCD Waveform Register 56.
LCD
0x58
8
read-write
n
0x0
0x0
BPALCD56
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD56
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD56
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD56
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD56
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD56
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD56
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD56
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF57
LCD Waveform Register 57.
0x59
8
read-write
n
0x0
0x0
BPALCD57
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD57
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD57
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD57
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD57
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD57
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD57
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD57
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF58
LCD Waveform Register 58.
0x5A
8
read-write
n
0x0
0x0
BPALCD58
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD58
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD58
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD58
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD58
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD58
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD58
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD58
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF59
LCD Waveform Register 59.
0x5B
8
read-write
n
0x0
0x0
BPALCD59
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD59
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD59
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD59
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD59
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD59
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD59
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD59
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF59TO56
LCD Waveform register
LCD
0x58
32
read-write
n
0x0
0x0
WF56
no description available
0
8
read-write
WF57
no description available
8
8
read-write
WF58
no description available
16
8
read-write
WF59
no description available
24
8
read-write
WF6
LCD Waveform Register 6.
0x26
8
read-write
n
0x0
0x0
BPALCD6
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD6
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD6
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD6
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD6
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD6
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD6
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD6
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF60
LCD Waveform Register 60.
LCD
0x5C
8
read-write
n
0x0
0x0
BPALCD60
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD60
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD60
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD60
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD60
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD60
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD60
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD60
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF61
LCD Waveform Register 61.
0x5D
8
read-write
n
0x0
0x0
BPALCD61
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD61
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD61
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD61
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD61
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD61
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD61
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD61
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF62
LCD Waveform Register 62.
0x5E
8
read-write
n
0x0
0x0
BPALCD62
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD62
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD62
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD62
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD62
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD62
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD62
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD62
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF63
LCD Waveform Register 63.
0x5F
8
read-write
n
0x0
0x0
BPALCD63
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD63
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD63
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD63
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD63
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD63
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD63
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD63
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF63TO60
LCD Waveform register
LCD
0x5C
32
read-write
n
0x0
0x0
WF60
no description available
0
8
read-write
WF61
no description available
8
8
read-write
WF62
no description available
16
8
read-write
WF63
no description available
24
8
read-write
WF7
LCD Waveform Register 7.
0x27
8
read-write
n
0x0
0x0
BPALCD7
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD7
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD7
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD7
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD7
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD7
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD7
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD7
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF7TO4
LCD Waveform register
LCD
0x24
32
read-write
n
0x0
0x0
WF4
no description available
0
8
read-write
WF5
no description available
8
8
read-write
WF6
no description available
16
8
read-write
WF7
no description available
24
8
read-write
WF8
LCD Waveform Register 8.
LCD
0x28
8
read-write
n
0x0
0x0
BPALCD8
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD8
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD8
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD8
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD8
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD8
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD8
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD8
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
WF9
LCD Waveform Register 9.
0x29
8
read-write
n
0x0
0x0
BPALCD9
no description available
0
1
read-write
0
LCD segment off or LCD backplane inactive for phase A
#0
1
LCD segment on or LCD backplane active for phase A
#1
BPBLCD9
no description available
1
1
read-write
0
LCD segment off or LCD backplane inactive for phase B
#0
1
LCD segment on or LCD backplane active for phase B
#1
BPCLCD9
no description available
2
1
read-write
0
LCD segment off or LCD backplane inactive for phase C
#0
1
LCD segment on or LCD backplane active for phase C
#1
BPDLCD9
no description available
3
1
read-write
0
LCD segment off or LCD backplane inactive for phase D
#0
1
LCD segment on or LCD backplane active for phase D
#1
BPELCD9
no description available
4
1
read-write
0
LCD segment off or LCD backplane inactive for phase E
#0
1
LCD segment on or LCD backplane active for phase E
#1
BPFLCD9
no description available
5
1
read-write
0
LCD segment off or LCD backplane inactive for phase F
#0
1
LCD segment on or LCD backplane active for phase F
#1
BPGLCD9
no description available
6
1
read-write
0
LCD segment off or LCD backplane inactive for phase G
#0
1
LCD segment on or LCD backplane active for phase G
#1
BPHLCD9
no description available
7
1
read-write
0
LCD segment off or LCD backplane inactive for phase H
#0
1
LCD segment on or LCD backplane active for phase H
#1
LLWU
Low leakage wakeup unit
LLWU
0x0
0x0
0xA
registers
n
LLWU
12
F1
LLWU Flag 1 register
0x5
8
read-write
n
0x0
0x0
WUF0
Wakeup Flag For LLWU_P0
0
1
read-write
0
LLWU_P0 input was not a wakeup source
#0
1
LLWU_P0 input was a wakeup source
#1
WUF1
Wakeup Flag For LLWU_P1
1
1
read-write
0
LLWU_P1 input was not a wakeup source
#0
1
LLWU_P1 input was a wakeup source
#1
WUF2
Wakeup Flag For LLWU_P2
2
1
read-write
0
LLWU_P2 input was not a wakeup source
#0
1
LLWU_P2 input was a wakeup source
#1
WUF3
Wakeup Flag For LLWU_P3
3
1
read-write
0
LLWU_P3 input was not a wake-up source
#0
1
LLWU_P3 input was a wake-up source
#1
WUF4
Wakeup Flag For LLWU_P4
4
1
read-write
0
LLWU_P4 input was not a wakeup source
#0
1
LLWU_P4 input was a wakeup source
#1
WUF5
Wakeup Flag For LLWU_P5
5
1
read-write
0
LLWU_P5 input was not a wakeup source
#0
1
LLWU_P5 input was a wakeup source
#1
WUF6
Wakeup Flag For LLWU_P6
6
1
read-write
0
LLWU_P6 input was not a wakeup source
#0
1
LLWU_P6 input was a wakeup source
#1
WUF7
Wakeup Flag For LLWU_P7
7
1
read-write
0
LLWU_P7 input was not a wakeup source
#0
1
LLWU_P7 input was a wakeup source
#1
F2
LLWU Flag 2 register
0x6
8
read-write
n
0x0
0x0
WUF10
Wakeup Flag For LLWU_P10
2
1
read-write
0
LLWU_P10 input was not a wakeup source
#0
1
LLWU_P10 input was a wakeup source
#1
WUF11
Wakeup Flag For LLWU_P11
3
1
read-write
0
LLWU_P11 input was not a wakeup source
#0
1
LLWU_P11 input was a wakeup source
#1
WUF12
Wakeup Flag For LLWU_P12
4
1
read-write
0
LLWU_P12 input was not a wakeup source
#0
1
LLWU_P12 input was a wakeup source
#1
WUF13
Wakeup Flag For LLWU_P13
5
1
read-write
0
LLWU_P13 input was not a wakeup source
#0
1
LLWU_P13 input was a wakeup source
#1
WUF14
Wakeup Flag For LLWU_P14
6
1
read-write
0
LLWU_P14 input was not a wakeup source
#0
1
LLWU_P14 input was a wakeup source
#1
WUF15
Wakeup Flag For LLWU_P15
7
1
read-write
0
LLWU_P15 input was not a wakeup source
#0
1
LLWU_P15 input was a wakeup source
#1
WUF8
Wakeup Flag For LLWU_P8
0
1
read-write
0
LLWU_P8 input was not a wakeup source
#0
1
LLWU_P8 input was a wakeup source
#1
WUF9
Wakeup Flag For LLWU_P9
1
1
read-write
0
LLWU_P9 input was not a wakeup source
#0
1
LLWU_P9 input was a wakeup source
#1
F3
LLWU Flag 3 register
0x7
8
read-only
n
0x0
0x0
MWUF0
Wakeup flag For module 0
0
1
read-only
0
Module 0 input was not a wakeup source
#0
1
Module 0 input was a wakeup source
#1
MWUF1
Wakeup flag For module 1
1
1
read-only
0
Module 1 input was not a wakeup source
#0
1
Module 1 input was a wakeup source
#1
MWUF2
Wakeup flag For module 2
2
1
read-only
0
Module 2 input was not a wakeup source
#0
1
Module 2 input was a wakeup source
#1
MWUF3
Wakeup flag For module 3
3
1
read-only
0
Module 3 input was not a wakeup source
#0
1
Module 3 input was a wakeup source
#1
MWUF4
Wakeup flag For module 4
4
1
read-only
0
Module 4 input was not a wakeup source
#0
1
Module 4 input was a wakeup source
#1
MWUF5
Wakeup flag For module 5
5
1
read-only
0
Module 5 input was not a wakeup source
#0
1
Module 5 input was a wakeup source
#1
MWUF6
Wakeup flag For module 6
6
1
read-only
0
Module 6 input was not a wakeup source
#0
1
Module 6 input was a wakeup source
#1
MWUF7
Wakeup flag For module 7
7
1
read-only
0
Module 7 input was not a wakeup source
#0
1
Module 7 input was a wakeup source
#1
FILT1
LLWU Pin Filter 1 register
0x8
8
read-write
n
0x0
0x0
FILTE
Digital Filter On External Pin
5
2
read-write
00
Filter disabled
#00
01
Filter posedge detect enabled
#01
10
Filter negedge detect enabled
#10
11
Filter any edge detect enabled
#11
FILTF
Filter Detect Flag
7
1
read-write
0
Pin Filter 1 was not a wakeup source
#0
1
Pin Filter 1 was a wakeup source
#1
FILTSEL
Filter Pin Select
0
4
read-write
0000
Select LLWU_P0 for filter
#0000
1111
Select LLWU_P15 for filter
#1111
FILT2
LLWU Pin Filter 2 register
0x9
8
read-write
n
0x0
0x0
FILTE
Digital Filter On External Pin
5
2
read-write
00
Filter disabled
#00
01
Filter posedge detect enabled
#01
10
Filter negedge detect enabled
#10
11
Filter any edge detect enabled
#11
FILTF
Filter Detect Flag
7
1
read-write
0
Pin Filter 2 was not a wakeup source
#0
1
Pin Filter 2 was a wakeup source
#1
FILTSEL
Filter Pin Select
0
4
read-write
0000
Select LLWU_P0 for filter
#0000
1111
Select LLWU_P15 for filter
#1111
ME
LLWU Module Enable register
0x4
8
read-write
n
0x0
0x0
WUME0
Wakeup Module Enable For Module 0
0
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME1
Wakeup Module Enable for Module 1
1
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME2
Wakeup Module Enable For Module 2
2
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME3
Wakeup Module Enable For Module 3
3
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME4
Wakeup Module Enable For Module 4
4
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME5
Wakeup Module Enable For Module 5
5
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME6
Wakeup Module Enable For Module 6
6
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
WUME7
Wakeup Module Enable For Module 7
7
1
read-write
0
Internal module flag not used as wakeup source
#0
1
Internal module flag used as wakeup source
#1
PE1
LLWU Pin Enable 1 register
0x0
8
read-write
n
0x0
0x0
WUPE0
Wakeup Pin Enable For LLWU_P0
0
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE1
Wakeup Pin Enable For LLWU_P1
2
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE2
Wakeup Pin Enable For LLWU_P2
4
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE3
Wakeup Pin Enable For LLWU_P3
6
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
PE2
LLWU Pin Enable 2 register
0x1
8
read-write
n
0x0
0x0
WUPE4
Wakeup Pin Enable For LLWU_P4
0
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE5
Wakeup Pin Enable For LLWU_P5
2
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE6
Wakeup Pin Enable For LLWU_P6
4
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE7
Wakeup Pin Enable For LLWU_P7
6
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
PE3
LLWU Pin Enable 3 register
0x2
8
read-write
n
0x0
0x0
WUPE10
Wakeup Pin Enable For LLWU_P10
4
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE11
Wakeup Pin Enable For LLWU_P11
6
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE8
Wakeup Pin Enable For LLWU_P8
0
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE9
Wakeup Pin Enable For LLWU_P9
2
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
PE4
LLWU Pin Enable 4 register
0x3
8
read-write
n
0x0
0x0
WUPE12
Wakeup Pin Enable For LLWU_P12
0
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE13
Wakeup Pin Enable For LLWU_P13
2
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE14
Wakeup Pin Enable For LLWU_P14
4
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
WUPE15
Wakeup Pin Enable For LLWU_P15
6
2
read-write
00
External input pin disabled as wakeup input
#00
01
External input pin enabled with rising edge detection
#01
10
External input pin enabled with falling edge detection
#10
11
External input pin enabled with any change detection
#11
LPTMR
Low Power Timer
LPTMR
0x0
0x0
0x10
registers
n
LPTMR
30
CMR
Low Power Timer Compare Register
0x8
32
read-write
n
0x0
0x0
COMPARE
Compare Value
0
16
read-write
CNR
Low Power Timer Counter Register
0xC
32
read-write
n
0x0
0x0
COUNTER
Counter Value
0
16
read-write
CSR
Low Power Timer Control Status Register
0x0
32
read-write
n
0x0
0x0
TCF
Timer Compare Flag
7
1
read-write
0
The value of CNR is not equal to CMR and increments.
#0
1
The value of CNR is equal to CMR and increments.
#1
TEN
Timer Enable
0
1
read-write
0
LPTMR is disabled and internal logic is reset.
#0
1
LPTMR is enabled.
#1
TFC
Timer Free-Running Counter
2
1
read-write
0
CNR is reset whenever TCF is set.
#0
1
CNR is reset on overflow.
#1
TIE
Timer Interrupt Enable
6
1
read-write
0
Timer interrupt disabled.
#0
1
Timer interrupt enabled.
#1
TMS
Timer Mode Select
1
1
read-write
0
Time Counter mode.
#0
1
Pulse Counter mode.
#1
TPP
Timer Pin Polarity
3
1
read-write
0
Pulse Counter input source is active-high, and the CNR will increment on the rising-edge.
#0
1
Pulse Counter input source is active-low, and the CNR will increment on the falling-edge.
#1
TPS
Timer Pin Select
4
2
read-write
00
Pulse counter input 0 is selected.
#00
01
Pulse counter input 1 is selected.
#01
10
Pulse counter input 2 is selected.
#10
11
Pulse counter input 3 is selected.
#11
PSR
Low Power Timer Prescale Register
0x4
32
read-write
n
0x0
0x0
PBYP
Prescaler Bypass
2
1
read-write
0
Prescaler/glitch filter is enabled.
#0
1
Prescaler/glitch filter is bypassed.
#1
PCS
Prescaler Clock Select
0
2
read-write
00
Prescaler/glitch filter clock 0 selected.
#00
01
Prescaler/glitch filter clock 1 selected.
#01
10
Prescaler/glitch filter clock 2 selected.
#10
11
Prescaler/glitch filter clock 3 selected.
#11
PRESCALE
Prescale Value
3
4
read-write
0000
Prescaler divides the prescaler clock by 2; glitch filter does not support this configuration.
#0000
0001
Prescaler divides the prescaler clock by 4; glitch filter recognizes change on input pin after 2 rising clock edges.
#0001
0010
Prescaler divides the prescaler clock by 8; glitch filter recognizes change on input pin after 4 rising clock edges.
#0010
0011
Prescaler divides the prescaler clock by 16; glitch filter recognizes change on input pin after 8 rising clock edges.
#0011
0100
Prescaler divides the prescaler clock by 32; glitch filter recognizes change on input pin after 16 rising clock edges.
#0100
0101
Prescaler divides the prescaler clock by 64; glitch filter recognizes change on input pin after 32 rising clock edges.
#0101
0110
Prescaler divides the prescaler clock by 128; glitch filter recognizes change on input pin after 64 rising clock edges.
#0110
0111
Prescaler divides the prescaler clock by 256; glitch filter recognizes change on input pin after 128 rising clock edges.
#0111
1000
Prescaler divides the prescaler clock by 512; glitch filter recognizes change on input pin after 256 rising clock edges.
#1000
1001
Prescaler divides the prescaler clock by 1024; glitch filter recognizes change on input pin after 512 rising clock edges.
#1001
1010
Prescaler divides the prescaler clock by 2048; glitch filter recognizes change on input pin after 1024 rising clock edges.
#1010
1011
Prescaler divides the prescaler clock by 4096; glitch filter recognizes change on input pin after 2048 rising clock edges.
#1011
1100
Prescaler divides the prescaler clock by 8192; glitch filter recognizes change on input pin after 4096 rising clock edges.
#1100
1101
Prescaler divides the prescaler clock by 16,384; glitch filter recognizes change on input pin after 8192 rising clock edges.
#1101
1110
Prescaler divides the prescaler clock by 32,768; glitch filter recognizes change on input pin after 16,384 rising clock edges.
#1110
1111
Prescaler divides the prescaler clock by 65,536; glitch filter recognizes change on input pin after 32,768 rising clock edges.
#1111
MCG
Multipurpose Clock Generator module
MCG
0x0
0x0
0xF
registers
n
MCG
28
ATCVH
MCG Auto Trim Compare Value High Register
0xA
8
read-write
n
0x0
0x0
ATCVH
ATM Compare Value High
0
8
read-write
ATCVL
MCG Auto Trim Compare Value Low Register
0xB
8
read-write
n
0x0
0x0
ATCVL
ATM Compare Value Low
0
8
read-write
C1
MCG Control 1 Register
0x0
8
read-write
n
0x0
0x0
CLKS
Clock Source Select
6
2
read-write
00
Encoding 0 - Output of FLL or PLL is selected (depends on PLLS control bit).
#00
01
Encoding 1 - Internal reference clock is selected.
#01
10
Encoding 2 - External reference clock is selected.
#10
11
Encoding 3 - Reserved.
#11
FRDIV
FLL External Reference Divider
3
3
read-write
000
If RANGE = 0 , Divide Factor is 1; for all other RANGE values, Divide Factor is 32.
#000
001
If RANGE = 0 , Divide Factor is 2; for all other RANGE values, Divide Factor is 64.
#001
010
If RANGE = 0 , Divide Factor is 4; for all other RANGE values, Divide Factor is 128.
#010
011
If RANGE = 0 , Divide Factor is 8; for all other RANGE values, Divide Factor is 256.
#011
100
If RANGE = 0 , Divide Factor is 16; for all other RANGE values, Divide Factor is 512.
#100
101
If RANGE = 0 , Divide Factor is 32; for all other RANGE values, Divide Factor is 1024.
#101
110
If RANGE = 0 , Divide Factor is 64; for all other RANGE values, Divide Factor is 1280 .
#110
111
If RANGE = 0 , Divide Factor is 128; for all other RANGE values, Divide Factor is 1536 .
#111
IRCLKEN
Internal Reference Clock Enable
1
1
read-write
0
MCGIRCLK inactive.
#0
1
MCGIRCLK active.
#1
IREFS
Internal Reference Select
2
1
read-write
0
External reference clock is selected.
#0
1
The slow internal reference clock is selected.
#1
IREFSTEN
Internal Reference Stop Enable
0
1
read-write
0
Internal reference clock is disabled in Stop mode.
#0
1
Internal reference clock is enabled in Stop mode if IRCLKEN is set or if MCG is in FEI, FBI, or BLPI modes before entering Stop mode.
#1
C2
MCG Control 2 Register
0x1
8
read-write
n
0x0
0x0
EREFS0
External Reference Select
2
1
read-write
0
External reference clock requested.
#0
1
Oscillator requested.
#1
HGO0
High Gain Oscillator Select
3
1
read-write
0
Configure crystal oscillator for low-power operation.
#0
1
Configure crystal oscillator for high-gain operation.
#1
IRCS
Internal Reference Clock Select
0
1
read-write
0
Slow internal reference clock selected.
#0
1
Fast internal reference clock selected.
#1
LOCRE0
Loss of Clock Reset Enable
7
1
read-write
0
Interrupt request is generated on a loss of OSC0 external reference clock.
#0
1
Generate a reset request on a loss of OSC0 external reference clock.
#1
LP
Low Power Select
1
1
read-write
0
FLL or PLL is not disabled in bypass modes.
#0
1
FLL or PLL is disabled in bypass modes (lower power)
#1
RANGE0
Frequency Range Select
4
2
read-write
00
Encoding 0 - Low frequency range selected for the crystal oscillator .
#00
01
Encoding 1 - High frequency range selected for the crystal oscillator .
#01
C3
MCG Control 3 Register
0x2
8
read-write
n
0x0
0x0
SCTRIM
Slow Internal Reference Clock Trim Setting
0
8
read-write
C4
MCG Control 4 Register
0x3
8
read-write
n
0x0
0x0
DMX32
DCO Maximum Frequency with 32.768 kHz Reference
7
1
read-write
0
DCO has a default range of 25%.
#0
1
DCO is fine-tuned for maximum frequency with 32.768 kHz reference.
#1
DRST_DRS
DCO Range Select
5
2
read-write
00
Encoding 0 - Low range (reset default).
#00
01
Encoding 1 - Mid range.
#01
10
Encoding 2 - Mid-high range.
#10
11
Encoding 3 - High range.
#11
FCTRIM
Fast Internal Reference Clock Trim Setting
1
4
read-write
SCFTRIM
Slow Internal Reference Clock Fine Trim
0
1
read-write
C5
MCG Control 5 Register
0x4
8
read-write
n
0x0
0x0
PLLCLKEN0
PLL Clock Enable
6
1
read-write
0
MCGPLLCLK is inactive.
#0
1
MCGPLLCLK is active.
#1
PLLSTEN0
PLL Stop Enable
5
1
read-write
0
MCGPLLCLK is disabled in any of the Stop modes.
#0
1
MCGPLLCLK is enabled if system is in Normal Stop mode.
#1
C6
MCG Control 6 Register
0x5
8
read-write
n
0x0
0x0
CHGPMP_BIAS
Directly controls the PLL Charge Pump Current. Appropiate selection of this value is imperative to ensure stable operation of the PLL closed loop system. The default value for this field is set to 5'b01000 out of reset which generates a nominal 750nA charge pump current (lcp).
0
5
read-only
CME0
Clock Monitor Enable
5
1
read-write
0
External clock monitor is disabled for OSC0.
#0
1
External clock monitor is enabled for OSC0.
#1
LOLIE0
Loss of Lock Interrrupt Enable
7
1
read-write
0
No interrupt request is generated on loss of lock.
#0
1
Generate an interrupt request on loss of lock.
#1
PLLS
PLL Select
6
1
read-write
0
FLL is selected.
#0
1
PLL is selected (PLL reference clock must be in the range of 31.25-39.0625 KHz prior to setting the PLLS bit).
#1
C7
MCG Control 7 Register
0xC
8
read-write
n
0x0
0x0
OSCSEL
MCG OSC Clock Select
0
1
read-write
0
Selects Oscillator (OSCCLK).
#0
1
Selects 32 kHz RTC Oscillator.
#1
PLL32KREFSEL
MCG PLL 32Khz Reference Clock Select
6
2
read-write
00
Selects 32 kHz RTC Oscillator.
#00
01
Selects 32 kHz IRC.
#01
10
Selects FLL FRDIV clock.
#10
C8
MCG Control 8 Register
0xD
8
read-write
n
0x0
0x0
CME1
Clock Monitor Enable1
5
1
read-write
0
External clock monitor is disabled for RTC clock.
#0
1
External clock monitor is enabled for RTC clock.
#1
COARSE_LOLIE
Loss of Coarse Lock Interrrupt Enable
4
1
read-write
0
No interrupt request is generated on coarse loss of lock.
#0
1
Generate an interrupt request on coarse loss of lock.
#1
LOCRE1
Loss of Clock Reset Enable
7
1
read-write
0
Interrupt request is generated on a loss of RTC external reference clock.
#0
1
Generate a reset request on a loss of RTC external reference clock
#1
LOCS1
RTC Loss of Clock Status
0
1
read-write
0
Loss of RTC has not occur.
#0
1
Loss of RTC has occur
#1
LOLRE
PLL Loss of Lock Reset Enable
6
1
read-write
0
Interrupt request is generated on a PLL loss of lock indication. The PLL loss of lock interrupt enable bit must also be set to generate the interrupt request.
#0
1
Generate a reset request on a PLL loss of lock indication.
#1
C9
MCG Control 9 Register
0xE
8
read-only
n
0x0
0x0
COARSE_LOCK
Coarse Lock Status
6
1
read-only
0
PLL is currently unlocked.
#0
1
PLL is currently locked after first sample.
#1
COARSE_LOLS
Coarse Loss of Lock Status
7
1
read-only
0
PLL has not lost lock since COARSE_LOLS was last cleared.
#0
1
PLL has lost lock since COARSE_LOLS was last cleared.
#1
S
MCG Status Register
0x6
8
read-write
n
0x0
0x0
CLKST
Clock Mode Status
2
2
read-only
00
Encoding 0 - Output of the FLL is selected (reset default).
#00
01
Encoding 1 - Internal reference clock is selected.
#01
10
Encoding 2 - External reference clock is selected.
#10
11
Encoding 3 - Output of the PLL is selected.
#11
IRCST
Internal Reference Clock Status
0
1
read-only
0
Source of internal reference clock is the slow clock (32 kHz IRC).
#0
1
Source of internal reference clock is the fast clock (4 MHz IRC).
#1
IREFST
Internal Reference Status
4
1
read-only
0
Source of FLL reference clock is the external reference clock.
#0
1
Source of FLL reference clock is the internal reference clock.
#1
LOCK0
Lock Status
6
1
read-only
0
PLL is currently unlocked.
#0
1
PLL is currently locked.
#1
LOLS0
Loss of Lock Status
7
1
read-write
0
PLL has not lost lock since LOLS 0 was last cleared.
#0
1
PLL has lost lock since LOLS 0 was last cleared.
#1
OSCINIT0
OSC Initialization
1
1
read-only
PLLST
PLL Select Status
5
1
read-only
0
Source of PLLS clock is FLL clock.
#0
1
Source of PLLS clock is PLL output clock.
#1
SC
MCG Status and Control Register
0x8
8
read-write
n
0x0
0x0
ATME
Automatic Trim Machine Enable
7
1
read-write
0
Auto Trim Machine disabled.
#0
1
Auto Trim Machine enabled.
#1
ATMF
Automatic Trim Machine Fail Flag
5
1
read-write
0
Automatic Trim Machine completed normally.
#0
1
Automatic Trim Machine failed.
#1
ATMS
Automatic Trim Machine Select
6
1
read-write
0
32 kHz Internal Reference Clock selected.
#0
1
4 MHz Internal Reference Clock selected.
#1
FCRDIV
Fast Clock Internal Reference Divider
1
3
read-write
000
Divide Factor is 1
#000
001
Divide Factor is 2.
#001
010
Divide Factor is 4.
#010
011
Divide Factor is 8.
#011
100
Divide Factor is 16
#100
101
Divide Factor is 32
#101
110
Divide Factor is 64
#110
111
Divide Factor is 128.
#111
FLTPRSRV
FLL Filter Preserve Enable
4
1
read-write
0
FLL filter and FLL frequency will reset on changes to currect clock mode.
#0
1
Fll filter and FLL frequency retain their previous values during new clock mode change.
#1
LOCS0
OSC0 Loss of Clock Status
0
1
read-write
0
Loss of OSC0 has not occurred.
#0
1
Loss of OSC0 has occurred.
#1
MCM
Core Platform Miscellaneous Control Module
MCM
0x0
0x8
0x7C
registers
n
CPO
Compute Operation Control Register
0x40
32
read-write
n
0x0
0x0
CPOACK
Compute Operation Acknowledge
1
1
read-only
0
Compute operation entry has not completed or compute operation exit has completed.
#0
1
Compute operation entry has completed or compute operation exit has not completed.
#1
CPOREQ
Compute Operation Request
0
1
read-write
0
Request is cleared.
#0
1
Request Compute Operation.
#1
CPOWOI
Compute Operation Wake-up on Interrupt
2
1
read-write
0
No effect.
#0
1
When set, the CPOREQ is cleared on any interrupt or exception vector fetch.
#1
MATCR
Master Attribute Configuration Register
0x80
32
read-write
n
0x0
0x0
ATC0
Attribute Configuration Master n
0
3
read-write
00x
Master attributes are statically forced to {privileged, secure}.
#00x
010
Master attributes are statically forced to {user, secure}.
#010
011
Master attributes are statically forced to {user, nonsecure}.
#011
100
Enable master attribute {privileged or user} and statically force {secure}.
#100
101
Enable master attribute {privileged or user} and statically force {nonsecure}.
#101
11x
Enable master attribute {privileged or user, secure or nonsecure}
#11x
ATC2
Attribute Configuration Master n
16
3
read-write
00x
Master attributes are statically forced to {privileged, secure}.
#00x
010
Master attributes are statically forced to {user, secure}.
#010
011
Master attributes are statically forced to {user, nonsecure}.
#011
100
Enable master attribute {privileged or user} and statically force {secure}.
#100
101
Enable master attribute {privileged or user} and statically force {nonsecure}.
#101
11x
Enable master attribute {privileged or user, secure or nonsecure}
#11x
RO0
Read-Only Master n
7
1
read-write
0
Writes to the ATCn are allowed.
#0
1
Writes to the ATCn are ignored.
#1
RO2
Read-Only Master n
23
1
read-write
0
Writes to the ATCn are allowed.
#0
1
Writes to the ATCn are ignored.
#1
PID
Process ID register
0x30
32
read-write
n
0x0
0x0
PID
M0_PID For MPU
0
8
read-write
0
Reserved for privileged secure tasks
#0
PLACR
Platform Control Register
0xC
32
read-write
n
0x0
0x0
ARB
Arbitration select
9
1
read-write
0
Fixed-priority arbitration for the crossbar masters
#0
1
Round-robin arbitration for the crossbar masters
#1
CFCC
Clear Flash Controller Cache
10
1
write-only
DFCC
Disable Flash Controller Cache
13
1
read-write
0
Enable flash controller cache.
#0
1
Disable flash controller cache.
#1
DFCDA
Disable Flash Controller Data Caching
11
1
read-write
0
Enable flash controller data caching
#0
1
Disable flash controller data caching.
#1
DFCIC
Disable Flash Controller Instruction Caching
12
1
read-write
0
Enable flash controller instruction caching.
#0
1
Disable flash controller instruction caching.
#1
DFCS
Disable Flash Controller Speculation
15
1
read-write
0
Enable flash controller speculation.
#0
1
Disable flash controller speculation.
#1
EFDS
Enable Flash Data Speculation
14
1
read-write
0
Disable flash data speculation.
#0
1
Enable flash data speculation.
#1
ESFC
Enable Stalling Flash Controller
16
1
read-write
0
Disable stalling flash controller when flash is busy.
#0
1
Enable stalling flash controller when flash is busy.
#1
PLAMC
Crossbar Switch (AXBS) Master Configuration
0xA
16
read-only
n
0x0
0x0
AMC
Each bit in the AMC field indicates whether there is a corresponding connection to the AXBS master input port.
0
8
read-only
0
A bus master connection to AXBS input port n is absent
#0
1
A bus master connection to AXBS input port n is present
#1
PLASC
Crossbar Switch (AXBS) Slave Configuration
0x8
16
read-only
n
0x0
0x0
ASC
Each bit in the ASC field indicates whether there is a corresponding connection to the crossbar switch's slave input port.
0
8
read-only
0
A bus slave connection to AXBS input port n is absent.
#0
1
A bus slave connection to AXBS input port n is present.
#1
MPU
Memory protection unit
MPU
0x0
0x0
0x820
registers
n
CESR
Control/Error Status Register
0x0
32
read-write
n
0x0
0x0
HRL
Hardware Revision Level
16
4
read-only
NRGD
Number Of Region Descriptors
8
4
read-only
0000
8 region descriptors
#0000
0001
12 region descriptors
#0001
0010
16 region descriptors
#0010
NSP
Number Of Slave Ports
12
4
read-only
SPERR
Slave Port n Error
30
2
read-write
0
No error has occurred for slave port n.
#0
1
An error has occurred for slave port n.
#1
VLD
Valid
0
1
read-write
0
MPU is disabled. All accesses from all bus masters are allowed.
#0
1
MPU is enabled
#1
EAR0
Error Address Register, slave port n
0x20
32
read-only
n
0x0
0x0
EADDR
Error Address
0
32
read-only
EAR1
Error Address Register, slave port n
0x38
32
read-only
n
0x0
0x0
EADDR
Error Address
0
32
read-only
EDR0
Error Detail Register, slave port n
0x28
32
read-only
n
0x0
0x0
EACD
Error Access Control Detail
16
16
read-only
EATTR
Error Attributes
1
3
read-only
000
User mode, instruction access
#000
001
User mode, data access
#001
010
Supervisor mode, instruction access
#010
011
Supervisor mode, data access
#011
EMN
Error Master Number
4
4
read-only
EPID
Error Process Identification
8
8
read-only
ERW
Error Read/Write
0
1
read-only
0
Read
#0
1
Write
#1
EDR1
Error Detail Register, slave port n
0x44
32
read-only
n
0x0
0x0
EACD
Error Access Control Detail
16
16
read-only
EATTR
Error Attributes
1
3
read-only
000
User mode, instruction access
#000
001
User mode, data access
#001
010
Supervisor mode, instruction access
#010
011
Supervisor mode, data access
#011
EMN
Error Master Number
4
4
read-only
EPID
Error Process Identification
8
8
read-only
ERW
Error Read/Write
0
1
read-only
0
Read
#0
1
Write
#1
RGD0_WORD0
Region Descriptor n, Word 0
0x800
32
read-write
n
0x0
0x0
SRTADDR
Start Address
5
27
read-write
RGD0_WORD1
Region Descriptor n, Word 1
0x808
32
read-write
n
0x0
0x0
ENDADDR
End Address
5
27
read-write
RGD0_WORD2
Region Descriptor n, Word 2
0x810
32
read-write
n
0x0
0x0
M0PE
Bus Master 0 Process Identifier enable
5
1
read-write
M0SM
Bus Master 0 Supervisor Mode Access Control
3
2
read-write
M0UM
Bus Master 0 User Mode Access Control
0
3
read-write
M1PE
Bus Master 1 Process Identifier enable
11
1
read-write
M1SM
Bus Master 1 Supervisor Mode Access Control
9
2
read-write
M1UM
Bus Master 1 User Mode Access Control
6
3
read-write
M2PE
Bus Master 2 Process Identifier Enable
17
1
read-write
M2SM
Bus Master 2 Supervisor Mode Access Control
15
2
read-write
M2UM
Bus Master 2 User Mode Access control
12
3
read-write
M3PE
Bus Master 3 Process Identifier Enable
23
1
read-write
0
Do not include the process identifier in the evaluation
#0
1
Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation
#1
M3SM
Bus Master 3 Supervisor Mode Access Control
21
2
read-write
00
r/w/x; read, write and execute allowed
#00
01
r/x; read and execute allowed, but no write
#01
10
r/w; read and write allowed, but no execute
#10
11
Same as User mode defined in M3UM
#11
M3UM
Bus Master 3 User Mode Access Control
18
3
read-write
0
An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
#0
1
Allows the given access type to occur
#1
M4RE
Bus Master 4 Read Enable
25
1
read-write
0
Bus master 4 reads terminate with an access error and the read is not performed
#0
1
Bus master 4 reads allowed
#1
M4WE
Bus Master 4 Write Enable
24
1
read-write
0
Bus master 4 writes terminate with an access error and the write is not performed
#0
1
Bus master 4 writes allowed
#1
M5RE
Bus Master 5 Read Enable
27
1
read-write
0
Bus master 5 reads terminate with an access error and the read is not performed
#0
1
Bus master 5 reads allowed
#1
M5WE
Bus Master 5 Write Enable
26
1
read-write
0
Bus master 5 writes terminate with an access error and the write is not performed
#0
1
Bus master 5 writes allowed
#1
M6RE
Bus Master 6 Read Enable
29
1
read-write
0
Bus master 6 reads terminate with an access error and the read is not performed
#0
1
Bus master 6 reads allowed
#1
M6WE
Bus Master 6 Write Enable
28
1
read-write
0
Bus master 6 writes terminate with an access error and the write is not performed
#0
1
Bus master 6 writes allowed
#1
M7RE
Bus Master 7 Read Enable
31
1
read-write
0
Bus master 7 reads terminate with an access error and the read is not performed
#0
1
Bus master 7 reads allowed
#1
M7WE
Bus Master 7 Write Enable
30
1
read-write
0
Bus master 7 writes terminate with an access error and the write is not performed
#0
1
Bus master 7 writes allowed
#1
RGD0_WORD3
Region Descriptor n, Word 3
0x818
32
read-write
n
0x0
0x0
PID
Process Identifier
24
8
read-write
PIDMASK
Process Identifier Mask
16
8
read-write
VLD
Valid
0
1
read-write
0
Region descriptor is invalid
#0
1
Region descriptor is valid
#1
RGD1_WORD0
Region Descriptor n, Word 0
0xC10
32
read-write
n
0x0
0x0
SRTADDR
Start Address
5
27
read-write
RGD1_WORD1
Region Descriptor n, Word 1
0xC1C
32
read-write
n
0x0
0x0
ENDADDR
End Address
5
27
read-write
RGD1_WORD2
Region Descriptor n, Word 2
0xC28
32
read-write
n
0x0
0x0
M0PE
Bus Master 0 Process Identifier enable
5
1
read-write
M0SM
Bus Master 0 Supervisor Mode Access Control
3
2
read-write
M0UM
Bus Master 0 User Mode Access Control
0
3
read-write
M1PE
Bus Master 1 Process Identifier enable
11
1
read-write
M1SM
Bus Master 1 Supervisor Mode Access Control
9
2
read-write
M1UM
Bus Master 1 User Mode Access Control
6
3
read-write
M2PE
Bus Master 2 Process Identifier Enable
17
1
read-write
M2SM
Bus Master 2 Supervisor Mode Access Control
15
2
read-write
M2UM
Bus Master 2 User Mode Access control
12
3
read-write
M3PE
Bus Master 3 Process Identifier Enable
23
1
read-write
0
Do not include the process identifier in the evaluation
#0
1
Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation
#1
M3SM
Bus Master 3 Supervisor Mode Access Control
21
2
read-write
00
r/w/x; read, write and execute allowed
#00
01
r/x; read and execute allowed, but no write
#01
10
r/w; read and write allowed, but no execute
#10
11
Same as User mode defined in M3UM
#11
M3UM
Bus Master 3 User Mode Access Control
18
3
read-write
0
An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
#0
1
Allows the given access type to occur
#1
M4RE
Bus Master 4 Read Enable
25
1
read-write
0
Bus master 4 reads terminate with an access error and the read is not performed
#0
1
Bus master 4 reads allowed
#1
M4WE
Bus Master 4 Write Enable
24
1
read-write
0
Bus master 4 writes terminate with an access error and the write is not performed
#0
1
Bus master 4 writes allowed
#1
M5RE
Bus Master 5 Read Enable
27
1
read-write
0
Bus master 5 reads terminate with an access error and the read is not performed
#0
1
Bus master 5 reads allowed
#1
M5WE
Bus Master 5 Write Enable
26
1
read-write
0
Bus master 5 writes terminate with an access error and the write is not performed
#0
1
Bus master 5 writes allowed
#1
M6RE
Bus Master 6 Read Enable
29
1
read-write
0
Bus master 6 reads terminate with an access error and the read is not performed
#0
1
Bus master 6 reads allowed
#1
M6WE
Bus Master 6 Write Enable
28
1
read-write
0
Bus master 6 writes terminate with an access error and the write is not performed
#0
1
Bus master 6 writes allowed
#1
M7RE
Bus Master 7 Read Enable
31
1
read-write
0
Bus master 7 reads terminate with an access error and the read is not performed
#0
1
Bus master 7 reads allowed
#1
M7WE
Bus Master 7 Write Enable
30
1
read-write
0
Bus master 7 writes terminate with an access error and the write is not performed
#0
1
Bus master 7 writes allowed
#1
RGD1_WORD3
Region Descriptor n, Word 3
0xC34
32
read-write
n
0x0
0x0
PID
Process Identifier
24
8
read-write
PIDMASK
Process Identifier Mask
16
8
read-write
VLD
Valid
0
1
read-write
0
Region descriptor is invalid
#0
1
Region descriptor is valid
#1
RGD2_WORD0
Region Descriptor n, Word 0
0x1030
32
read-write
n
0x0
0x0
SRTADDR
Start Address
5
27
read-write
RGD2_WORD1
Region Descriptor n, Word 1
0x1040
32
read-write
n
0x0
0x0
ENDADDR
End Address
5
27
read-write
RGD2_WORD2
Region Descriptor n, Word 2
0x1050
32
read-write
n
0x0
0x0
M0PE
Bus Master 0 Process Identifier enable
5
1
read-write
M0SM
Bus Master 0 Supervisor Mode Access Control
3
2
read-write
M0UM
Bus Master 0 User Mode Access Control
0
3
read-write
M1PE
Bus Master 1 Process Identifier enable
11
1
read-write
M1SM
Bus Master 1 Supervisor Mode Access Control
9
2
read-write
M1UM
Bus Master 1 User Mode Access Control
6
3
read-write
M2PE
Bus Master 2 Process Identifier Enable
17
1
read-write
M2SM
Bus Master 2 Supervisor Mode Access Control
15
2
read-write
M2UM
Bus Master 2 User Mode Access control
12
3
read-write
M3PE
Bus Master 3 Process Identifier Enable
23
1
read-write
0
Do not include the process identifier in the evaluation
#0
1
Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation
#1
M3SM
Bus Master 3 Supervisor Mode Access Control
21
2
read-write
00
r/w/x; read, write and execute allowed
#00
01
r/x; read and execute allowed, but no write
#01
10
r/w; read and write allowed, but no execute
#10
11
Same as User mode defined in M3UM
#11
M3UM
Bus Master 3 User Mode Access Control
18
3
read-write
0
An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
#0
1
Allows the given access type to occur
#1
M4RE
Bus Master 4 Read Enable
25
1
read-write
0
Bus master 4 reads terminate with an access error and the read is not performed
#0
1
Bus master 4 reads allowed
#1
M4WE
Bus Master 4 Write Enable
24
1
read-write
0
Bus master 4 writes terminate with an access error and the write is not performed
#0
1
Bus master 4 writes allowed
#1
M5RE
Bus Master 5 Read Enable
27
1
read-write
0
Bus master 5 reads terminate with an access error and the read is not performed
#0
1
Bus master 5 reads allowed
#1
M5WE
Bus Master 5 Write Enable
26
1
read-write
0
Bus master 5 writes terminate with an access error and the write is not performed
#0
1
Bus master 5 writes allowed
#1
M6RE
Bus Master 6 Read Enable
29
1
read-write
0
Bus master 6 reads terminate with an access error and the read is not performed
#0
1
Bus master 6 reads allowed
#1
M6WE
Bus Master 6 Write Enable
28
1
read-write
0
Bus master 6 writes terminate with an access error and the write is not performed
#0
1
Bus master 6 writes allowed
#1
M7RE
Bus Master 7 Read Enable
31
1
read-write
0
Bus master 7 reads terminate with an access error and the read is not performed
#0
1
Bus master 7 reads allowed
#1
M7WE
Bus Master 7 Write Enable
30
1
read-write
0
Bus master 7 writes terminate with an access error and the write is not performed
#0
1
Bus master 7 writes allowed
#1
RGD2_WORD3
Region Descriptor n, Word 3
0x1060
32
read-write
n
0x0
0x0
PID
Process Identifier
24
8
read-write
PIDMASK
Process Identifier Mask
16
8
read-write
VLD
Valid
0
1
read-write
0
Region descriptor is invalid
#0
1
Region descriptor is valid
#1
RGD3_WORD0
Region Descriptor n, Word 0
0x1460
32
read-write
n
0x0
0x0
SRTADDR
Start Address
5
27
read-write
RGD3_WORD1
Region Descriptor n, Word 1
0x1474
32
read-write
n
0x0
0x0
ENDADDR
End Address
5
27
read-write
RGD3_WORD2
Region Descriptor n, Word 2
0x1488
32
read-write
n
0x0
0x0
M0PE
Bus Master 0 Process Identifier enable
5
1
read-write
M0SM
Bus Master 0 Supervisor Mode Access Control
3
2
read-write
M0UM
Bus Master 0 User Mode Access Control
0
3
read-write
M1PE
Bus Master 1 Process Identifier enable
11
1
read-write
M1SM
Bus Master 1 Supervisor Mode Access Control
9
2
read-write
M1UM
Bus Master 1 User Mode Access Control
6
3
read-write
M2PE
Bus Master 2 Process Identifier Enable
17
1
read-write
M2SM
Bus Master 2 Supervisor Mode Access Control
15
2
read-write
M2UM
Bus Master 2 User Mode Access control
12
3
read-write
M3PE
Bus Master 3 Process Identifier Enable
23
1
read-write
0
Do not include the process identifier in the evaluation
#0
1
Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation
#1
M3SM
Bus Master 3 Supervisor Mode Access Control
21
2
read-write
00
r/w/x; read, write and execute allowed
#00
01
r/x; read and execute allowed, but no write
#01
10
r/w; read and write allowed, but no execute
#10
11
Same as User mode defined in M3UM
#11
M3UM
Bus Master 3 User Mode Access Control
18
3
read-write
0
An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
#0
1
Allows the given access type to occur
#1
M4RE
Bus Master 4 Read Enable
25
1
read-write
0
Bus master 4 reads terminate with an access error and the read is not performed
#0
1
Bus master 4 reads allowed
#1
M4WE
Bus Master 4 Write Enable
24
1
read-write
0
Bus master 4 writes terminate with an access error and the write is not performed
#0
1
Bus master 4 writes allowed
#1
M5RE
Bus Master 5 Read Enable
27
1
read-write
0
Bus master 5 reads terminate with an access error and the read is not performed
#0
1
Bus master 5 reads allowed
#1
M5WE
Bus Master 5 Write Enable
26
1
read-write
0
Bus master 5 writes terminate with an access error and the write is not performed
#0
1
Bus master 5 writes allowed
#1
M6RE
Bus Master 6 Read Enable
29
1
read-write
0
Bus master 6 reads terminate with an access error and the read is not performed
#0
1
Bus master 6 reads allowed
#1
M6WE
Bus Master 6 Write Enable
28
1
read-write
0
Bus master 6 writes terminate with an access error and the write is not performed
#0
1
Bus master 6 writes allowed
#1
M7RE
Bus Master 7 Read Enable
31
1
read-write
0
Bus master 7 reads terminate with an access error and the read is not performed
#0
1
Bus master 7 reads allowed
#1
M7WE
Bus Master 7 Write Enable
30
1
read-write
0
Bus master 7 writes terminate with an access error and the write is not performed
#0
1
Bus master 7 writes allowed
#1
RGD3_WORD3
Region Descriptor n, Word 3
0x149C
32
read-write
n
0x0
0x0
PID
Process Identifier
24
8
read-write
PIDMASK
Process Identifier Mask
16
8
read-write
VLD
Valid
0
1
read-write
0
Region descriptor is invalid
#0
1
Region descriptor is valid
#1
RGD4_WORD0
Region Descriptor n, Word 0
0x18A0
32
read-write
n
0x0
0x0
SRTADDR
Start Address
5
27
read-write
RGD4_WORD1
Region Descriptor n, Word 1
0x18B8
32
read-write
n
0x0
0x0
ENDADDR
End Address
5
27
read-write
RGD4_WORD2
Region Descriptor n, Word 2
0x18D0
32
read-write
n
0x0
0x0
M0PE
Bus Master 0 Process Identifier enable
5
1
read-write
M0SM
Bus Master 0 Supervisor Mode Access Control
3
2
read-write
M0UM
Bus Master 0 User Mode Access Control
0
3
read-write
M1PE
Bus Master 1 Process Identifier enable
11
1
read-write
M1SM
Bus Master 1 Supervisor Mode Access Control
9
2
read-write
M1UM
Bus Master 1 User Mode Access Control
6
3
read-write
M2PE
Bus Master 2 Process Identifier Enable
17
1
read-write
M2SM
Bus Master 2 Supervisor Mode Access Control
15
2
read-write
M2UM
Bus Master 2 User Mode Access control
12
3
read-write
M3PE
Bus Master 3 Process Identifier Enable
23
1
read-write
0
Do not include the process identifier in the evaluation
#0
1
Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation
#1
M3SM
Bus Master 3 Supervisor Mode Access Control
21
2
read-write
00
r/w/x; read, write and execute allowed
#00
01
r/x; read and execute allowed, but no write
#01
10
r/w; read and write allowed, but no execute
#10
11
Same as User mode defined in M3UM
#11
M3UM
Bus Master 3 User Mode Access Control
18
3
read-write
0
An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
#0
1
Allows the given access type to occur
#1
M4RE
Bus Master 4 Read Enable
25
1
read-write
0
Bus master 4 reads terminate with an access error and the read is not performed
#0
1
Bus master 4 reads allowed
#1
M4WE
Bus Master 4 Write Enable
24
1
read-write
0
Bus master 4 writes terminate with an access error and the write is not performed
#0
1
Bus master 4 writes allowed
#1
M5RE
Bus Master 5 Read Enable
27
1
read-write
0
Bus master 5 reads terminate with an access error and the read is not performed
#0
1
Bus master 5 reads allowed
#1
M5WE
Bus Master 5 Write Enable
26
1
read-write
0
Bus master 5 writes terminate with an access error and the write is not performed
#0
1
Bus master 5 writes allowed
#1
M6RE
Bus Master 6 Read Enable
29
1
read-write
0
Bus master 6 reads terminate with an access error and the read is not performed
#0
1
Bus master 6 reads allowed
#1
M6WE
Bus Master 6 Write Enable
28
1
read-write
0
Bus master 6 writes terminate with an access error and the write is not performed
#0
1
Bus master 6 writes allowed
#1
M7RE
Bus Master 7 Read Enable
31
1
read-write
0
Bus master 7 reads terminate with an access error and the read is not performed
#0
1
Bus master 7 reads allowed
#1
M7WE
Bus Master 7 Write Enable
30
1
read-write
0
Bus master 7 writes terminate with an access error and the write is not performed
#0
1
Bus master 7 writes allowed
#1
RGD4_WORD3
Region Descriptor n, Word 3
0x18E8
32
read-write
n
0x0
0x0
PID
Process Identifier
24
8
read-write
PIDMASK
Process Identifier Mask
16
8
read-write
VLD
Valid
0
1
read-write
0
Region descriptor is invalid
#0
1
Region descriptor is valid
#1
RGD5_WORD0
Region Descriptor n, Word 0
0x1CF0
32
read-write
n
0x0
0x0
SRTADDR
Start Address
5
27
read-write
RGD5_WORD1
Region Descriptor n, Word 1
0x1D0C
32
read-write
n
0x0
0x0
ENDADDR
End Address
5
27
read-write
RGD5_WORD2
Region Descriptor n, Word 2
0x1D28
32
read-write
n
0x0
0x0
M0PE
Bus Master 0 Process Identifier enable
5
1
read-write
M0SM
Bus Master 0 Supervisor Mode Access Control
3
2
read-write
M0UM
Bus Master 0 User Mode Access Control
0
3
read-write
M1PE
Bus Master 1 Process Identifier enable
11
1
read-write
M1SM
Bus Master 1 Supervisor Mode Access Control
9
2
read-write
M1UM
Bus Master 1 User Mode Access Control
6
3
read-write
M2PE
Bus Master 2 Process Identifier Enable
17
1
read-write
M2SM
Bus Master 2 Supervisor Mode Access Control
15
2
read-write
M2UM
Bus Master 2 User Mode Access control
12
3
read-write
M3PE
Bus Master 3 Process Identifier Enable
23
1
read-write
0
Do not include the process identifier in the evaluation
#0
1
Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation
#1
M3SM
Bus Master 3 Supervisor Mode Access Control
21
2
read-write
00
r/w/x; read, write and execute allowed
#00
01
r/x; read and execute allowed, but no write
#01
10
r/w; read and write allowed, but no execute
#10
11
Same as User mode defined in M3UM
#11
M3UM
Bus Master 3 User Mode Access Control
18
3
read-write
0
An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
#0
1
Allows the given access type to occur
#1
M4RE
Bus Master 4 Read Enable
25
1
read-write
0
Bus master 4 reads terminate with an access error and the read is not performed
#0
1
Bus master 4 reads allowed
#1
M4WE
Bus Master 4 Write Enable
24
1
read-write
0
Bus master 4 writes terminate with an access error and the write is not performed
#0
1
Bus master 4 writes allowed
#1
M5RE
Bus Master 5 Read Enable
27
1
read-write
0
Bus master 5 reads terminate with an access error and the read is not performed
#0
1
Bus master 5 reads allowed
#1
M5WE
Bus Master 5 Write Enable
26
1
read-write
0
Bus master 5 writes terminate with an access error and the write is not performed
#0
1
Bus master 5 writes allowed
#1
M6RE
Bus Master 6 Read Enable
29
1
read-write
0
Bus master 6 reads terminate with an access error and the read is not performed
#0
1
Bus master 6 reads allowed
#1
M6WE
Bus Master 6 Write Enable
28
1
read-write
0
Bus master 6 writes terminate with an access error and the write is not performed
#0
1
Bus master 6 writes allowed
#1
M7RE
Bus Master 7 Read Enable
31
1
read-write
0
Bus master 7 reads terminate with an access error and the read is not performed
#0
1
Bus master 7 reads allowed
#1
M7WE
Bus Master 7 Write Enable
30
1
read-write
0
Bus master 7 writes terminate with an access error and the write is not performed
#0
1
Bus master 7 writes allowed
#1
RGD5_WORD3
Region Descriptor n, Word 3
0x1D44
32
read-write
n
0x0
0x0
PID
Process Identifier
24
8
read-write
PIDMASK
Process Identifier Mask
16
8
read-write
VLD
Valid
0
1
read-write
0
Region descriptor is invalid
#0
1
Region descriptor is valid
#1
RGD6_WORD0
Region Descriptor n, Word 0
0x2150
32
read-write
n
0x0
0x0
SRTADDR
Start Address
5
27
read-write
RGD6_WORD1
Region Descriptor n, Word 1
0x2170
32
read-write
n
0x0
0x0
ENDADDR
End Address
5
27
read-write
RGD6_WORD2
Region Descriptor n, Word 2
0x2190
32
read-write
n
0x0
0x0
M0PE
Bus Master 0 Process Identifier enable
5
1
read-write
M0SM
Bus Master 0 Supervisor Mode Access Control
3
2
read-write
M0UM
Bus Master 0 User Mode Access Control
0
3
read-write
M1PE
Bus Master 1 Process Identifier enable
11
1
read-write
M1SM
Bus Master 1 Supervisor Mode Access Control
9
2
read-write
M1UM
Bus Master 1 User Mode Access Control
6
3
read-write
M2PE
Bus Master 2 Process Identifier Enable
17
1
read-write
M2SM
Bus Master 2 Supervisor Mode Access Control
15
2
read-write
M2UM
Bus Master 2 User Mode Access control
12
3
read-write
M3PE
Bus Master 3 Process Identifier Enable
23
1
read-write
0
Do not include the process identifier in the evaluation
#0
1
Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation
#1
M3SM
Bus Master 3 Supervisor Mode Access Control
21
2
read-write
00
r/w/x; read, write and execute allowed
#00
01
r/x; read and execute allowed, but no write
#01
10
r/w; read and write allowed, but no execute
#10
11
Same as User mode defined in M3UM
#11
M3UM
Bus Master 3 User Mode Access Control
18
3
read-write
0
An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
#0
1
Allows the given access type to occur
#1
M4RE
Bus Master 4 Read Enable
25
1
read-write
0
Bus master 4 reads terminate with an access error and the read is not performed
#0
1
Bus master 4 reads allowed
#1
M4WE
Bus Master 4 Write Enable
24
1
read-write
0
Bus master 4 writes terminate with an access error and the write is not performed
#0
1
Bus master 4 writes allowed
#1
M5RE
Bus Master 5 Read Enable
27
1
read-write
0
Bus master 5 reads terminate with an access error and the read is not performed
#0
1
Bus master 5 reads allowed
#1
M5WE
Bus Master 5 Write Enable
26
1
read-write
0
Bus master 5 writes terminate with an access error and the write is not performed
#0
1
Bus master 5 writes allowed
#1
M6RE
Bus Master 6 Read Enable
29
1
read-write
0
Bus master 6 reads terminate with an access error and the read is not performed
#0
1
Bus master 6 reads allowed
#1
M6WE
Bus Master 6 Write Enable
28
1
read-write
0
Bus master 6 writes terminate with an access error and the write is not performed
#0
1
Bus master 6 writes allowed
#1
M7RE
Bus Master 7 Read Enable
31
1
read-write
0
Bus master 7 reads terminate with an access error and the read is not performed
#0
1
Bus master 7 reads allowed
#1
M7WE
Bus Master 7 Write Enable
30
1
read-write
0
Bus master 7 writes terminate with an access error and the write is not performed
#0
1
Bus master 7 writes allowed
#1
RGD6_WORD3
Region Descriptor n, Word 3
0x21B0
32
read-write
n
0x0
0x0
PID
Process Identifier
24
8
read-write
PIDMASK
Process Identifier Mask
16
8
read-write
VLD
Valid
0
1
read-write
0
Region descriptor is invalid
#0
1
Region descriptor is valid
#1
RGD7_WORD0
Region Descriptor n, Word 0
0x25C0
32
read-write
n
0x0
0x0
SRTADDR
Start Address
5
27
read-write
RGD7_WORD1
Region Descriptor n, Word 1
0x25E4
32
read-write
n
0x0
0x0
ENDADDR
End Address
5
27
read-write
RGD7_WORD2
Region Descriptor n, Word 2
0x2608
32
read-write
n
0x0
0x0
M0PE
Bus Master 0 Process Identifier enable
5
1
read-write
M0SM
Bus Master 0 Supervisor Mode Access Control
3
2
read-write
M0UM
Bus Master 0 User Mode Access Control
0
3
read-write
M1PE
Bus Master 1 Process Identifier enable
11
1
read-write
M1SM
Bus Master 1 Supervisor Mode Access Control
9
2
read-write
M1UM
Bus Master 1 User Mode Access Control
6
3
read-write
M2PE
Bus Master 2 Process Identifier Enable
17
1
read-write
M2SM
Bus Master 2 Supervisor Mode Access Control
15
2
read-write
M2UM
Bus Master 2 User Mode Access control
12
3
read-write
M3PE
Bus Master 3 Process Identifier Enable
23
1
read-write
0
Do not include the process identifier in the evaluation
#0
1
Include the process identifier and mask (RGDn_WORD3) in the region hit evaluation
#1
M3SM
Bus Master 3 Supervisor Mode Access Control
21
2
read-write
00
r/w/x; read, write and execute allowed
#00
01
r/x; read and execute allowed, but no write
#01
10
r/w; read and write allowed, but no execute
#10
11
Same as User mode defined in M3UM
#11
M3UM
Bus Master 3 User Mode Access Control
18
3
read-write
0
An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
#0
1
Allows the given access type to occur
#1
M4RE
Bus Master 4 Read Enable
25
1
read-write
0
Bus master 4 reads terminate with an access error and the read is not performed
#0
1
Bus master 4 reads allowed
#1
M4WE
Bus Master 4 Write Enable
24
1
read-write
0
Bus master 4 writes terminate with an access error and the write is not performed
#0
1
Bus master 4 writes allowed
#1
M5RE
Bus Master 5 Read Enable
27
1
read-write
0
Bus master 5 reads terminate with an access error and the read is not performed
#0
1
Bus master 5 reads allowed
#1
M5WE
Bus Master 5 Write Enable
26
1
read-write
0
Bus master 5 writes terminate with an access error and the write is not performed
#0
1
Bus master 5 writes allowed
#1
M6RE
Bus Master 6 Read Enable
29
1
read-write
0
Bus master 6 reads terminate with an access error and the read is not performed
#0
1
Bus master 6 reads allowed
#1
M6WE
Bus Master 6 Write Enable
28
1
read-write
0
Bus master 6 writes terminate with an access error and the write is not performed
#0
1
Bus master 6 writes allowed
#1
M7RE
Bus Master 7 Read Enable
31
1
read-write
0
Bus master 7 reads terminate with an access error and the read is not performed
#0
1
Bus master 7 reads allowed
#1
M7WE
Bus Master 7 Write Enable
30
1
read-write
0
Bus master 7 writes terminate with an access error and the write is not performed
#0
1
Bus master 7 writes allowed
#1
RGD7_WORD3
Region Descriptor n, Word 3
0x262C
32
read-write
n
0x0
0x0
PID
Process Identifier
24
8
read-write
PIDMASK
Process Identifier Mask
16
8
read-write
VLD
Valid
0
1
read-write
0
Region descriptor is invalid
#0
1
Region descriptor is valid
#1
RGDAAC0
Region Descriptor Alternate Access Control n
0x1000
32
read-write
n
0x0
0x0
M0PE
Bus Master 0 Process Identifier Enable
5
1
read-write
M0SM
Bus Master 0 Supervisor Mode Access Control
3
2
read-write
M0UM
Bus Master 0 User Mode Access Control
0
3
read-write
M1PE
Bus Master 1 Process Identifier Enable
11
1
read-write
M1SM
Bus Master 1 Supervisor Mode Access Control
9
2
read-write
M1UM
Bus Master 1 User Mode Access Control
6
3
read-write
M2PE
Bus Master 2 Process Identifier Enable
17
1
read-write
M2SM
Bus Master 2 Supervisor Mode Access Control
15
2
read-write
M2UM
Bus Master 2 User Mode Access Control
12
3
read-write
M3PE
Bus Master 3 Process Identifier Enable
23
1
read-write
0
Do not include the process identifier in the evaluation
#0
1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
#1
M3SM
Bus Master 3 Supervisor Mode Access Control
21
2
read-write
00
r/w/x; read, write and execute allowed
#00
01
r/x; read and execute allowed, but no write
#01
10
r/w; read and write allowed, but no execute
#10
11
Same as User mode defined in M3UM
#11
M3UM
Bus Master 3 User Mode Access Control
18
3
read-write
0
An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
#0
1
Allows the given access type to occur
#1
M4RE
Bus Master 4 Read Enable
25
1
read-write
0
Bus master 4 reads terminate with an access error and the read is not performed
#0
1
Bus master 4 reads allowed
#1
M4WE
Bus Master 4 Write Enable
24
1
read-write
0
Bus master 4 writes terminate with an access error and the write is not performed
#0
1
Bus master 4 writes allowed
#1
M5RE
Bus Master 5 Read Enable
27
1
read-write
0
Bus master 5 reads terminate with an access error and the read is not performed
#0
1
Bus master 5 reads allowed
#1
M5WE
Bus Master 5 Write Enable
26
1
read-write
0
Bus master 5 writes terminate with an access error and the write is not performed
#0
1
Bus master 5 writes allowed
#1
M6RE
Bus Master 6 Read Enable
29
1
read-write
0
Bus master 6 reads terminate with an access error and the read is not performed
#0
1
Bus master 6 reads allowed
#1
M6WE
Bus Master 6 Write Enable
28
1
read-write
0
Bus master 6 writes terminate with an access error and the write is not performed
#0
1
Bus master 6 writes allowed
#1
M7RE
Bus Master 7 Read Enable
31
1
read-write
0
Bus master 7 reads terminate with an access error and the read is not performed
#0
1
Bus master 7 reads allowed
#1
M7WE
Bus Master 7 Write Enable
30
1
read-write
0
Bus master 7 writes terminate with an access error and the write is not performed
#0
1
Bus master 7 writes allowed
#1
RGDAAC1
Region Descriptor Alternate Access Control n
0x1804
32
read-write
n
0x0
0x0
M0PE
Bus Master 0 Process Identifier Enable
5
1
read-write
M0SM
Bus Master 0 Supervisor Mode Access Control
3
2
read-write
M0UM
Bus Master 0 User Mode Access Control
0
3
read-write
M1PE
Bus Master 1 Process Identifier Enable
11
1
read-write
M1SM
Bus Master 1 Supervisor Mode Access Control
9
2
read-write
M1UM
Bus Master 1 User Mode Access Control
6
3
read-write
M2PE
Bus Master 2 Process Identifier Enable
17
1
read-write
M2SM
Bus Master 2 Supervisor Mode Access Control
15
2
read-write
M2UM
Bus Master 2 User Mode Access Control
12
3
read-write
M3PE
Bus Master 3 Process Identifier Enable
23
1
read-write
0
Do not include the process identifier in the evaluation
#0
1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
#1
M3SM
Bus Master 3 Supervisor Mode Access Control
21
2
read-write
00
r/w/x; read, write and execute allowed
#00
01
r/x; read and execute allowed, but no write
#01
10
r/w; read and write allowed, but no execute
#10
11
Same as User mode defined in M3UM
#11
M3UM
Bus Master 3 User Mode Access Control
18
3
read-write
0
An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
#0
1
Allows the given access type to occur
#1
M4RE
Bus Master 4 Read Enable
25
1
read-write
0
Bus master 4 reads terminate with an access error and the read is not performed
#0
1
Bus master 4 reads allowed
#1
M4WE
Bus Master 4 Write Enable
24
1
read-write
0
Bus master 4 writes terminate with an access error and the write is not performed
#0
1
Bus master 4 writes allowed
#1
M5RE
Bus Master 5 Read Enable
27
1
read-write
0
Bus master 5 reads terminate with an access error and the read is not performed
#0
1
Bus master 5 reads allowed
#1
M5WE
Bus Master 5 Write Enable
26
1
read-write
0
Bus master 5 writes terminate with an access error and the write is not performed
#0
1
Bus master 5 writes allowed
#1
M6RE
Bus Master 6 Read Enable
29
1
read-write
0
Bus master 6 reads terminate with an access error and the read is not performed
#0
1
Bus master 6 reads allowed
#1
M6WE
Bus Master 6 Write Enable
28
1
read-write
0
Bus master 6 writes terminate with an access error and the write is not performed
#0
1
Bus master 6 writes allowed
#1
M7RE
Bus Master 7 Read Enable
31
1
read-write
0
Bus master 7 reads terminate with an access error and the read is not performed
#0
1
Bus master 7 reads allowed
#1
M7WE
Bus Master 7 Write Enable
30
1
read-write
0
Bus master 7 writes terminate with an access error and the write is not performed
#0
1
Bus master 7 writes allowed
#1
RGDAAC2
Region Descriptor Alternate Access Control n
0x200C
32
read-write
n
0x0
0x0
M0PE
Bus Master 0 Process Identifier Enable
5
1
read-write
M0SM
Bus Master 0 Supervisor Mode Access Control
3
2
read-write
M0UM
Bus Master 0 User Mode Access Control
0
3
read-write
M1PE
Bus Master 1 Process Identifier Enable
11
1
read-write
M1SM
Bus Master 1 Supervisor Mode Access Control
9
2
read-write
M1UM
Bus Master 1 User Mode Access Control
6
3
read-write
M2PE
Bus Master 2 Process Identifier Enable
17
1
read-write
M2SM
Bus Master 2 Supervisor Mode Access Control
15
2
read-write
M2UM
Bus Master 2 User Mode Access Control
12
3
read-write
M3PE
Bus Master 3 Process Identifier Enable
23
1
read-write
0
Do not include the process identifier in the evaluation
#0
1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
#1
M3SM
Bus Master 3 Supervisor Mode Access Control
21
2
read-write
00
r/w/x; read, write and execute allowed
#00
01
r/x; read and execute allowed, but no write
#01
10
r/w; read and write allowed, but no execute
#10
11
Same as User mode defined in M3UM
#11
M3UM
Bus Master 3 User Mode Access Control
18
3
read-write
0
An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
#0
1
Allows the given access type to occur
#1
M4RE
Bus Master 4 Read Enable
25
1
read-write
0
Bus master 4 reads terminate with an access error and the read is not performed
#0
1
Bus master 4 reads allowed
#1
M4WE
Bus Master 4 Write Enable
24
1
read-write
0
Bus master 4 writes terminate with an access error and the write is not performed
#0
1
Bus master 4 writes allowed
#1
M5RE
Bus Master 5 Read Enable
27
1
read-write
0
Bus master 5 reads terminate with an access error and the read is not performed
#0
1
Bus master 5 reads allowed
#1
M5WE
Bus Master 5 Write Enable
26
1
read-write
0
Bus master 5 writes terminate with an access error and the write is not performed
#0
1
Bus master 5 writes allowed
#1
M6RE
Bus Master 6 Read Enable
29
1
read-write
0
Bus master 6 reads terminate with an access error and the read is not performed
#0
1
Bus master 6 reads allowed
#1
M6WE
Bus Master 6 Write Enable
28
1
read-write
0
Bus master 6 writes terminate with an access error and the write is not performed
#0
1
Bus master 6 writes allowed
#1
M7RE
Bus Master 7 Read Enable
31
1
read-write
0
Bus master 7 reads terminate with an access error and the read is not performed
#0
1
Bus master 7 reads allowed
#1
M7WE
Bus Master 7 Write Enable
30
1
read-write
0
Bus master 7 writes terminate with an access error and the write is not performed
#0
1
Bus master 7 writes allowed
#1
RGDAAC3
Region Descriptor Alternate Access Control n
0x2818
32
read-write
n
0x0
0x0
M0PE
Bus Master 0 Process Identifier Enable
5
1
read-write
M0SM
Bus Master 0 Supervisor Mode Access Control
3
2
read-write
M0UM
Bus Master 0 User Mode Access Control
0
3
read-write
M1PE
Bus Master 1 Process Identifier Enable
11
1
read-write
M1SM
Bus Master 1 Supervisor Mode Access Control
9
2
read-write
M1UM
Bus Master 1 User Mode Access Control
6
3
read-write
M2PE
Bus Master 2 Process Identifier Enable
17
1
read-write
M2SM
Bus Master 2 Supervisor Mode Access Control
15
2
read-write
M2UM
Bus Master 2 User Mode Access Control
12
3
read-write
M3PE
Bus Master 3 Process Identifier Enable
23
1
read-write
0
Do not include the process identifier in the evaluation
#0
1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
#1
M3SM
Bus Master 3 Supervisor Mode Access Control
21
2
read-write
00
r/w/x; read, write and execute allowed
#00
01
r/x; read and execute allowed, but no write
#01
10
r/w; read and write allowed, but no execute
#10
11
Same as User mode defined in M3UM
#11
M3UM
Bus Master 3 User Mode Access Control
18
3
read-write
0
An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
#0
1
Allows the given access type to occur
#1
M4RE
Bus Master 4 Read Enable
25
1
read-write
0
Bus master 4 reads terminate with an access error and the read is not performed
#0
1
Bus master 4 reads allowed
#1
M4WE
Bus Master 4 Write Enable
24
1
read-write
0
Bus master 4 writes terminate with an access error and the write is not performed
#0
1
Bus master 4 writes allowed
#1
M5RE
Bus Master 5 Read Enable
27
1
read-write
0
Bus master 5 reads terminate with an access error and the read is not performed
#0
1
Bus master 5 reads allowed
#1
M5WE
Bus Master 5 Write Enable
26
1
read-write
0
Bus master 5 writes terminate with an access error and the write is not performed
#0
1
Bus master 5 writes allowed
#1
M6RE
Bus Master 6 Read Enable
29
1
read-write
0
Bus master 6 reads terminate with an access error and the read is not performed
#0
1
Bus master 6 reads allowed
#1
M6WE
Bus Master 6 Write Enable
28
1
read-write
0
Bus master 6 writes terminate with an access error and the write is not performed
#0
1
Bus master 6 writes allowed
#1
M7RE
Bus Master 7 Read Enable
31
1
read-write
0
Bus master 7 reads terminate with an access error and the read is not performed
#0
1
Bus master 7 reads allowed
#1
M7WE
Bus Master 7 Write Enable
30
1
read-write
0
Bus master 7 writes terminate with an access error and the write is not performed
#0
1
Bus master 7 writes allowed
#1
RGDAAC4
Region Descriptor Alternate Access Control n
0x3028
32
read-write
n
0x0
0x0
M0PE
Bus Master 0 Process Identifier Enable
5
1
read-write
M0SM
Bus Master 0 Supervisor Mode Access Control
3
2
read-write
M0UM
Bus Master 0 User Mode Access Control
0
3
read-write
M1PE
Bus Master 1 Process Identifier Enable
11
1
read-write
M1SM
Bus Master 1 Supervisor Mode Access Control
9
2
read-write
M1UM
Bus Master 1 User Mode Access Control
6
3
read-write
M2PE
Bus Master 2 Process Identifier Enable
17
1
read-write
M2SM
Bus Master 2 Supervisor Mode Access Control
15
2
read-write
M2UM
Bus Master 2 User Mode Access Control
12
3
read-write
M3PE
Bus Master 3 Process Identifier Enable
23
1
read-write
0
Do not include the process identifier in the evaluation
#0
1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
#1
M3SM
Bus Master 3 Supervisor Mode Access Control
21
2
read-write
00
r/w/x; read, write and execute allowed
#00
01
r/x; read and execute allowed, but no write
#01
10
r/w; read and write allowed, but no execute
#10
11
Same as User mode defined in M3UM
#11
M3UM
Bus Master 3 User Mode Access Control
18
3
read-write
0
An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
#0
1
Allows the given access type to occur
#1
M4RE
Bus Master 4 Read Enable
25
1
read-write
0
Bus master 4 reads terminate with an access error and the read is not performed
#0
1
Bus master 4 reads allowed
#1
M4WE
Bus Master 4 Write Enable
24
1
read-write
0
Bus master 4 writes terminate with an access error and the write is not performed
#0
1
Bus master 4 writes allowed
#1
M5RE
Bus Master 5 Read Enable
27
1
read-write
0
Bus master 5 reads terminate with an access error and the read is not performed
#0
1
Bus master 5 reads allowed
#1
M5WE
Bus Master 5 Write Enable
26
1
read-write
0
Bus master 5 writes terminate with an access error and the write is not performed
#0
1
Bus master 5 writes allowed
#1
M6RE
Bus Master 6 Read Enable
29
1
read-write
0
Bus master 6 reads terminate with an access error and the read is not performed
#0
1
Bus master 6 reads allowed
#1
M6WE
Bus Master 6 Write Enable
28
1
read-write
0
Bus master 6 writes terminate with an access error and the write is not performed
#0
1
Bus master 6 writes allowed
#1
M7RE
Bus Master 7 Read Enable
31
1
read-write
0
Bus master 7 reads terminate with an access error and the read is not performed
#0
1
Bus master 7 reads allowed
#1
M7WE
Bus Master 7 Write Enable
30
1
read-write
0
Bus master 7 writes terminate with an access error and the write is not performed
#0
1
Bus master 7 writes allowed
#1
RGDAAC5
Region Descriptor Alternate Access Control n
0x383C
32
read-write
n
0x0
0x0
M0PE
Bus Master 0 Process Identifier Enable
5
1
read-write
M0SM
Bus Master 0 Supervisor Mode Access Control
3
2
read-write
M0UM
Bus Master 0 User Mode Access Control
0
3
read-write
M1PE
Bus Master 1 Process Identifier Enable
11
1
read-write
M1SM
Bus Master 1 Supervisor Mode Access Control
9
2
read-write
M1UM
Bus Master 1 User Mode Access Control
6
3
read-write
M2PE
Bus Master 2 Process Identifier Enable
17
1
read-write
M2SM
Bus Master 2 Supervisor Mode Access Control
15
2
read-write
M2UM
Bus Master 2 User Mode Access Control
12
3
read-write
M3PE
Bus Master 3 Process Identifier Enable
23
1
read-write
0
Do not include the process identifier in the evaluation
#0
1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
#1
M3SM
Bus Master 3 Supervisor Mode Access Control
21
2
read-write
00
r/w/x; read, write and execute allowed
#00
01
r/x; read and execute allowed, but no write
#01
10
r/w; read and write allowed, but no execute
#10
11
Same as User mode defined in M3UM
#11
M3UM
Bus Master 3 User Mode Access Control
18
3
read-write
0
An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
#0
1
Allows the given access type to occur
#1
M4RE
Bus Master 4 Read Enable
25
1
read-write
0
Bus master 4 reads terminate with an access error and the read is not performed
#0
1
Bus master 4 reads allowed
#1
M4WE
Bus Master 4 Write Enable
24
1
read-write
0
Bus master 4 writes terminate with an access error and the write is not performed
#0
1
Bus master 4 writes allowed
#1
M5RE
Bus Master 5 Read Enable
27
1
read-write
0
Bus master 5 reads terminate with an access error and the read is not performed
#0
1
Bus master 5 reads allowed
#1
M5WE
Bus Master 5 Write Enable
26
1
read-write
0
Bus master 5 writes terminate with an access error and the write is not performed
#0
1
Bus master 5 writes allowed
#1
M6RE
Bus Master 6 Read Enable
29
1
read-write
0
Bus master 6 reads terminate with an access error and the read is not performed
#0
1
Bus master 6 reads allowed
#1
M6WE
Bus Master 6 Write Enable
28
1
read-write
0
Bus master 6 writes terminate with an access error and the write is not performed
#0
1
Bus master 6 writes allowed
#1
M7RE
Bus Master 7 Read Enable
31
1
read-write
0
Bus master 7 reads terminate with an access error and the read is not performed
#0
1
Bus master 7 reads allowed
#1
M7WE
Bus Master 7 Write Enable
30
1
read-write
0
Bus master 7 writes terminate with an access error and the write is not performed
#0
1
Bus master 7 writes allowed
#1
RGDAAC6
Region Descriptor Alternate Access Control n
0x4054
32
read-write
n
0x0
0x0
M0PE
Bus Master 0 Process Identifier Enable
5
1
read-write
M0SM
Bus Master 0 Supervisor Mode Access Control
3
2
read-write
M0UM
Bus Master 0 User Mode Access Control
0
3
read-write
M1PE
Bus Master 1 Process Identifier Enable
11
1
read-write
M1SM
Bus Master 1 Supervisor Mode Access Control
9
2
read-write
M1UM
Bus Master 1 User Mode Access Control
6
3
read-write
M2PE
Bus Master 2 Process Identifier Enable
17
1
read-write
M2SM
Bus Master 2 Supervisor Mode Access Control
15
2
read-write
M2UM
Bus Master 2 User Mode Access Control
12
3
read-write
M3PE
Bus Master 3 Process Identifier Enable
23
1
read-write
0
Do not include the process identifier in the evaluation
#0
1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
#1
M3SM
Bus Master 3 Supervisor Mode Access Control
21
2
read-write
00
r/w/x; read, write and execute allowed
#00
01
r/x; read and execute allowed, but no write
#01
10
r/w; read and write allowed, but no execute
#10
11
Same as User mode defined in M3UM
#11
M3UM
Bus Master 3 User Mode Access Control
18
3
read-write
0
An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
#0
1
Allows the given access type to occur
#1
M4RE
Bus Master 4 Read Enable
25
1
read-write
0
Bus master 4 reads terminate with an access error and the read is not performed
#0
1
Bus master 4 reads allowed
#1
M4WE
Bus Master 4 Write Enable
24
1
read-write
0
Bus master 4 writes terminate with an access error and the write is not performed
#0
1
Bus master 4 writes allowed
#1
M5RE
Bus Master 5 Read Enable
27
1
read-write
0
Bus master 5 reads terminate with an access error and the read is not performed
#0
1
Bus master 5 reads allowed
#1
M5WE
Bus Master 5 Write Enable
26
1
read-write
0
Bus master 5 writes terminate with an access error and the write is not performed
#0
1
Bus master 5 writes allowed
#1
M6RE
Bus Master 6 Read Enable
29
1
read-write
0
Bus master 6 reads terminate with an access error and the read is not performed
#0
1
Bus master 6 reads allowed
#1
M6WE
Bus Master 6 Write Enable
28
1
read-write
0
Bus master 6 writes terminate with an access error and the write is not performed
#0
1
Bus master 6 writes allowed
#1
M7RE
Bus Master 7 Read Enable
31
1
read-write
0
Bus master 7 reads terminate with an access error and the read is not performed
#0
1
Bus master 7 reads allowed
#1
M7WE
Bus Master 7 Write Enable
30
1
read-write
0
Bus master 7 writes terminate with an access error and the write is not performed
#0
1
Bus master 7 writes allowed
#1
RGDAAC7
Region Descriptor Alternate Access Control n
0x4870
32
read-write
n
0x0
0x0
M0PE
Bus Master 0 Process Identifier Enable
5
1
read-write
M0SM
Bus Master 0 Supervisor Mode Access Control
3
2
read-write
M0UM
Bus Master 0 User Mode Access Control
0
3
read-write
M1PE
Bus Master 1 Process Identifier Enable
11
1
read-write
M1SM
Bus Master 1 Supervisor Mode Access Control
9
2
read-write
M1UM
Bus Master 1 User Mode Access Control
6
3
read-write
M2PE
Bus Master 2 Process Identifier Enable
17
1
read-write
M2SM
Bus Master 2 Supervisor Mode Access Control
15
2
read-write
M2UM
Bus Master 2 User Mode Access Control
12
3
read-write
M3PE
Bus Master 3 Process Identifier Enable
23
1
read-write
0
Do not include the process identifier in the evaluation
#0
1
Include the process identifier and mask (RGDn.RGDAAC) in the region hit evaluation
#1
M3SM
Bus Master 3 Supervisor Mode Access Control
21
2
read-write
00
r/w/x; read, write and execute allowed
#00
01
r/x; read and execute allowed, but no write
#01
10
r/w; read and write allowed, but no execute
#10
11
Same as User mode defined in M3UM
#11
M3UM
Bus Master 3 User Mode Access Control
18
3
read-write
0
An attempted access of that mode may be terminated with an access error (if not allowed by another descriptor) and the access not performed.
#0
1
Allows the given access type to occur
#1
M4RE
Bus Master 4 Read Enable
25
1
read-write
0
Bus master 4 reads terminate with an access error and the read is not performed
#0
1
Bus master 4 reads allowed
#1
M4WE
Bus Master 4 Write Enable
24
1
read-write
0
Bus master 4 writes terminate with an access error and the write is not performed
#0
1
Bus master 4 writes allowed
#1
M5RE
Bus Master 5 Read Enable
27
1
read-write
0
Bus master 5 reads terminate with an access error and the read is not performed
#0
1
Bus master 5 reads allowed
#1
M5WE
Bus Master 5 Write Enable
26
1
read-write
0
Bus master 5 writes terminate with an access error and the write is not performed
#0
1
Bus master 5 writes allowed
#1
M6RE
Bus Master 6 Read Enable
29
1
read-write
0
Bus master 6 reads terminate with an access error and the read is not performed
#0
1
Bus master 6 reads allowed
#1
M6WE
Bus Master 6 Write Enable
28
1
read-write
0
Bus master 6 writes terminate with an access error and the write is not performed
#0
1
Bus master 6 writes allowed
#1
M7RE
Bus Master 7 Read Enable
31
1
read-write
0
Bus master 7 reads terminate with an access error and the read is not performed
#0
1
Bus master 7 reads allowed
#1
M7WE
Bus Master 7 Write Enable
30
1
read-write
0
Bus master 7 writes terminate with an access error and the write is not performed
#0
1
Bus master 7 writes allowed
#1
MTB
Micro Trace Buffer
MTB
0x0
0x0
0x1000
registers
n
AUTHSTAT
Authentication Status Register
0xFB8
32
read-only
n
0x0
0x0
BIT0
no description available
0
1
read-only
BIT1
BIT1
1
1
read-only
BIT2
BIT2
2
1
read-only
BIT3
BIT3
3
1
read-only
BASE
MTB Base Register
0xC
32
read-only
n
0x0
0x0
BASEADDR
BASEADDR
0
32
read-only
COMPID0
Component ID Register
0x1FE0
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID1
Component ID Register
0x2FD4
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID2
Component ID Register
0x3FCC
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID3
Component ID Register
0x4FC8
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
DEVICEARCH
Device Architecture Register
0xFBC
32
read-only
n
0x0
0x0
DEVICEARCH
DEVICEARCH
0
32
read-only
DEVICECFG
Device Configuration Register
0xFC8
32
read-only
n
0x0
0x0
DEVICECFG
DEVICECFG
0
32
read-only
DEVICETYPID
Device Type Identifier Register
0xFCC
32
read-only
n
0x0
0x0
DEVICETYPID
DEVICETYPID
0
32
read-only
FLOW
MTB Flow Register
0x8
32
read-write
n
0x0
0x0
AUTOHALT
AUTOHALT
1
1
read-write
AUTOSTOP
AUTOSTOP
0
1
read-write
WATERMARK
WATERMARK[28:0]
3
29
read-write
LOCKACCESS
Lock Access Register
0xFB0
32
read-only
n
0x0
0x0
LOCKACCESS
no description available
0
32
read-only
LOCKSTAT
Lock Status Register
0xFB4
32
read-only
n
0x0
0x0
LOCKSTAT
LOCKSTAT
0
32
read-only
MASTER
MTB Master Register
0x4
32
read-write
n
0x0
0x0
EN
Main Trace Enable
31
1
read-write
HALTREQ
Halt Request
9
1
read-write
MASK
Mask
0
5
read-write
RAMPRIV
RAM Privilege
8
1
read-write
SFRWPRIV
Special Function Register Write Privilege
7
1
read-write
TSTARTEN
Trace Start Input Enable
5
1
read-write
TSTOPEN
Trace Stop Input Enable
6
1
read-write
MODECTRL
Integration Mode Control Register
0xF00
32
read-only
n
0x0
0x0
MODECTRL
MODECTRL
0
32
read-only
PERIPHID0
Peripheral ID Register
0x5F08
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID1
Peripheral ID Register
0x6EEC
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID2
Peripheral ID Register
0x7ED4
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID3
Peripheral ID Register
0x8EC0
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID4
Peripheral ID Register
0x1FA0
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID5
Peripheral ID Register
0x2F74
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID6
Peripheral ID Register
0x3F4C
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID7
Peripheral ID Register
0x4F28
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
POSITION
MTB Position Register
0x0
32
read-write
n
0x0
0x0
POINTER
Trace Packet Address Pointer[28:0]
3
29
read-write
WRAP
WRAP
2
1
read-write
TAGCLEAR
Claim TAG Clear Register
0xFA4
32
read-only
n
0x0
0x0
TAGCLEAR
TAGCLEAR
0
32
read-only
TAGSET
Claim TAG Set Register
0xFA0
32
read-only
n
0x0
0x0
TAGSET
TAGSET
0
32
read-only
MTBDWT
MTB data watchpoint and trace
MTBDWT
0x0
0x0
0x1000
registers
n
COMP0
MTB_DWT Comparator Register
0x40
32
read-write
n
0x0
0x0
COMP
Reference value for comparison
0
32
read-write
COMP1
MTB_DWT Comparator Register
0x70
32
read-write
n
0x0
0x0
COMP
Reference value for comparison
0
32
read-write
COMPID0
Component ID Register
0x1FE0
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID1
Component ID Register
0x2FD4
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID2
Component ID Register
0x3FCC
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID3
Component ID Register
0x4FC8
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
CTRL
MTB DWT Control Register
0x0
32
read-only
n
0x0
0x0
DWTCFGCTRL
DWT configuration controls
0
28
read-only
NUMCMP
Number of comparators
28
4
read-only
DEVICECFG
Device Configuration Register
0xFC8
32
read-only
n
0x0
0x0
DEVICECFG
DEVICECFG
0
32
read-only
DEVICETYPID
Device Type Identifier Register
0xFCC
32
read-only
n
0x0
0x0
DEVICETYPID
DEVICETYPID
0
32
read-only
FCT0
MTB_DWT Comparator Function Register 0
0x28
32
read-write
n
0x0
0x0
DATAVADDR0
Data Value Address 0
12
4
read-write
DATAVMATCH
Data Value Match
8
1
read-write
0
Perform address comparison.
#0
1
Perform data value comparison.
#1
DATAVSIZE
Data Value Size
10
2
read-write
00
Byte.
#00
01
Halfword.
#01
10
Word.
#10
11
Reserved. Any attempts to use this value results in UNPREDICTABLE behavior.
#11
FUNCTION
Function
0
4
read-write
0000
Disabled.
#0000
0100
Instruction fetch.
#0100
0101
Data operand read.
#0101
0110
Data operand write.
#0110
0111
Data operand (read + write).
#0111
MATCHED
Comparator match
24
1
read-only
0
No match.
#0
1
Match occurred.
#1
FCT1
MTB_DWT Comparator Function Register 1
0x38
32
read-write
n
0x0
0x0
FUNCTION
Function
0
4
read-write
0000
Disabled.
#0000
0100
Instruction fetch.
#0100
0101
Data operand read.
#0101
0110
Data operand write.
#0110
0111
Data operand (read + write).
#0111
MATCHED
Comparator match
24
1
read-only
0
No match.
#0
1
Match occurred.
#1
MASK0
MTB_DWT Comparator Mask Register
0x48
32
read-write
n
0x0
0x0
MASK
MASK
0
5
read-write
MASK1
MTB_DWT Comparator Mask Register
0x7C
32
read-write
n
0x0
0x0
MASK
MASK
0
5
read-write
PERIPHID0
Peripheral ID Register
0x5F08
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID1
Peripheral ID Register
0x6EEC
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID2
Peripheral ID Register
0x7ED4
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID3
Peripheral ID Register
0x8EC0
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID4
Peripheral ID Register
0x1FA0
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID5
Peripheral ID Register
0x2F74
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID6
Peripheral ID Register
0x3F4C
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID7
Peripheral ID Register
0x4F28
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
TBCTRL
MTB_DWT Trace Buffer Control Register
0x200
32
read-write
n
0x0
0x0
ACOMP0
Action based on Comparator 0 match
0
1
read-write
0
Trigger TSTOP based on the assertion of MTBDWT_FCT0[MATCHED].
#0
1
Trigger TSTART based on the assertion of MTBDWT_FCT0[MATCHED].
#1
ACOMP1
Action based on Comparator 1 match
1
1
read-write
0
Trigger TSTOP based on the assertion of MTBDWT_FCT1[MATCHED].
#0
1
Trigger TSTART based on the assertion of MTBDWT_FCT1[MATCHED].
#1
NUMCOMP
Number of Comparators
28
4
read-only
OSC
Oscillator
OSC
0x0
0x0
0x1
registers
n
CR
OSC Control Register
0x0
8
read-write
n
0x0
0x0
ERCLKEN
External Reference Enable
7
1
read-write
0
External reference clock is inactive.
#0
1
External reference clock is enabled.
#1
EREFSTEN
External Reference Stop Enable
5
1
read-write
0
External reference clock is disabled in Stop mode.
#0
1
External reference clock stays enabled in Stop mode if ERCLKEN is set before entering Stop mode.
#1
SC16P
Oscillator 16 pF Capacitor Load Configure
0
1
read-write
0
Disable the selection.
#0
1
Add 16 pF capacitor to the oscillator load.
#1
SC2P
Oscillator 2 pF Capacitor Load Configure
3
1
read-write
0
Disable the selection.
#0
1
Add 2 pF capacitor to the oscillator load.
#1
SC4P
Oscillator 4 pF Capacitor Load Configure
2
1
read-write
0
Disable the selection.
#0
1
Add 4 pF capacitor to the oscillator load.
#1
SC8P
Oscillator 8 pF Capacitor Load Configure
1
1
read-write
0
Disable the selection.
#0
1
Add 8 pF capacitor to the oscillator load.
#1
PIT0
Periodic Interrupt Timer
PIT
0x0
0x0
0x120
registers
n
PIT0_PIT1
11
CVAL0
Current Timer Value Register
0x208
32
read-only
n
0x0
0x0
TVL
Current Timer Value
0
32
read-only
CVAL1
Current Timer Value Register
0x31C
32
read-only
n
0x0
0x0
TVL
Current Timer Value
0
32
read-only
LDVAL0
Timer Load Value Register
0x200
32
read-write
n
0x0
0x0
TSV
Timer Start Value
0
32
read-write
LDVAL1
Timer Load Value Register
0x310
32
read-write
n
0x0
0x0
TSV
Timer Start Value
0
32
read-write
MCR
PIT Module Control Register
0x0
32
read-write
n
0x0
0x0
FRZ
Freeze
0
1
read-write
0
Timers continue to run in Debug mode.
#0
1
Timers are stopped in Debug mode.
#1
MDIS
Module Disable - (PIT section)
1
1
read-write
0
Clock for standard PIT timers is enabled.
#0
1
Clock for standard PIT timers is disabled.
#1
TCTRL0
Timer Control Register
0x210
32
read-write
n
0x0
0x0
CHN
Chain Mode
2
1
read-write
0
Timer is not chained.
#0
1
Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
#1
TEN
Timer Enable
0
1
read-write
0
Timer n is disabled.
#0
1
Timer n is enabled.
#1
TIE
Timer Interrupt Enable
1
1
read-write
0
Interrupt requests from Timer n are disabled.
#0
1
Interrupt will be requested whenever TIF is set.
#1
TCTRL1
Timer Control Register
0x328
32
read-write
n
0x0
0x0
CHN
Chain Mode
2
1
read-write
0
Timer is not chained.
#0
1
Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
#1
TEN
Timer Enable
0
1
read-write
0
Timer n is disabled.
#0
1
Timer n is enabled.
#1
TIE
Timer Interrupt Enable
1
1
read-write
0
Interrupt requests from Timer n are disabled.
#0
1
Interrupt will be requested whenever TIF is set.
#1
TFLG0
Timer Flag Register
0x218
32
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
0
1
read-write
0
Timeout has not yet occurred.
#0
1
Timeout has occurred.
#1
TFLG1
Timer Flag Register
0x334
32
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
0
1
read-write
0
Timeout has not yet occurred.
#0
1
Timeout has occurred.
#1
PIT1
Periodic Interrupt Timer
PIT
0x0
0x0
0x120
registers
n
PIT0_PIT1
11
CVAL0
Current Timer Value Register
0x208
32
read-only
n
0x0
0x0
TVL
Current Timer Value
0
32
read-only
CVAL1
Current Timer Value Register
0x31C
32
read-only
n
0x0
0x0
TVL
Current Timer Value
0
32
read-only
LDVAL0
Timer Load Value Register
0x200
32
read-write
n
0x0
0x0
TSV
Timer Start Value
0
32
read-write
LDVAL1
Timer Load Value Register
0x310
32
read-write
n
0x0
0x0
TSV
Timer Start Value
0
32
read-write
MCR
PIT Module Control Register
0x0
32
read-write
n
0x0
0x0
FRZ
Freeze
0
1
read-write
0
Timers continue to run in Debug mode.
#0
1
Timers are stopped in Debug mode.
#1
MDIS
Module Disable - (PIT section)
1
1
read-write
0
Clock for standard PIT timers is enabled.
#0
1
Clock for standard PIT timers is disabled.
#1
TCTRL0
Timer Control Register
0x210
32
read-write
n
0x0
0x0
CHN
Chain Mode
2
1
read-write
0
Timer is not chained.
#0
1
Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
#1
TEN
Timer Enable
0
1
read-write
0
Timer n is disabled.
#0
1
Timer n is enabled.
#1
TIE
Timer Interrupt Enable
1
1
read-write
0
Interrupt requests from Timer n are disabled.
#0
1
Interrupt will be requested whenever TIF is set.
#1
TCTRL1
Timer Control Register
0x328
32
read-write
n
0x0
0x0
CHN
Chain Mode
2
1
read-write
0
Timer is not chained.
#0
1
Timer is chained to previous timer. For example, for Channel 2, if this field is set, Timer 2 is chained to Timer 1.
#1
TEN
Timer Enable
0
1
read-write
0
Timer n is disabled.
#0
1
Timer n is enabled.
#1
TIE
Timer Interrupt Enable
1
1
read-write
0
Interrupt requests from Timer n are disabled.
#0
1
Interrupt will be requested whenever TIF is set.
#1
TFLG0
Timer Flag Register
0x218
32
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
0
1
read-write
0
Timeout has not yet occurred.
#0
1
Timeout has occurred.
#1
TFLG1
Timer Flag Register
0x334
32
read-write
n
0x0
0x0
TIF
Timer Interrupt Flag
0
1
read-write
0
Timeout has not yet occurred.
#0
1
Timeout has occurred.
#1
PMC
Power Management Controller
PMC
0x0
0x0
0x3
registers
n
PMC
6
LVDSC1
Low Voltage Detect Status And Control 1 register
0x0
8
read-write
n
0x0
0x0
LVDACK
Low-Voltage Detect Acknowledge
6
1
write-only
LVDF
Low-Voltage Detect Flag
7
1
read-only
0
Low-voltage event not detected
#0
1
Low-voltage event detected
#1
LVDIE
Low-Voltage Detect Interrupt Enable
5
1
read-write
0
Hardware interrupt disabled (use polling)
#0
1
Request a hardware interrupt when LVDF = 1
#1
LVDRE
Low-Voltage Detect Reset Enable
4
1
read-write
0
LVDF does not generate hardware resets
#0
1
Force an MCU reset when LVDF = 1
#1
LVDV
Low-Voltage Detect Voltage Select
0
2
read-write
00
Low trip point selected (V LVD = V LVDL )
#00
01
High trip point selected (V LVD = V LVDH )
#01
LVDSC2
Low Voltage Detect Status And Control 2 register
0x1
8
read-write
n
0x0
0x0
LVWACK
Low-Voltage Warning Acknowledge
6
1
write-only
LVWF
Low-Voltage Warning Flag
7
1
read-only
0
Low-voltage warning event not detected
#0
1
Low-voltage warning event detected
#1
LVWIE
Low-Voltage Warning Interrupt Enable
5
1
read-write
0
Hardware interrupt disabled (use polling)
#0
1
Request a hardware interrupt when LVWF = 1
#1
LVWV
Low-Voltage Warning Voltage Select
0
2
read-write
00
Low trip point selected (VLVW = VLVW1)
#00
01
Mid 1 trip point selected (VLVW = VLVW2)
#01
10
Mid 2 trip point selected (VLVW = VLVW3)
#10
11
High trip point selected (VLVW = VLVW4)
#11
REGSC
Regulator Status And Control register
0x2
8
read-write
n
0x0
0x0
ACKISO
Acknowledge Isolation
3
1
read-write
0
Peripherals and I/O pads are in normal run state.
#0
1
Certain peripherals and I/O pads are in an isolated and latched state.
#1
BGBDS
Bandgap Buffer Drive Select
1
1
read-write
0
Low drive
#0
1
High drive
#1
BGBE
Bandgap Buffer Enable
0
1
read-write
0
Bandgap buffer not enabled
#0
1
Bandgap buffer enabled
#1
BGEN
Bandgap Enable In VLPx Operation
4
1
read-write
0
Bandgap voltage reference is disabled in VLPx , and VLLSx modes.
#0
1
Bandgap voltage reference is enabled in VLPx , and VLLSx modes.
#1
REGONS
Regulator In Run Regulation Status
2
1
read-only
0
Regulator is in stop regulation or in transition to/from it
#0
1
Regulator is in run regulation
#1
PORTA
Pin Control and Interrupts
PORT
0x0
0x0
0xA4
registers
n
PTx
17
GPCHR
Global Pin Control High Register
0x84
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCLR
Global Pin Control Low Register
0x80
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
n
0x0
0x0
ISF
Interrupt Status Flag
0
32
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR0
Pin Control Register n
0x0
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR1
Pin Control Register n
0x4
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR2
Pin Control Register n
0xC
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR3
Pin Control Register n
0x18
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR4
Pin Control Register n
0x28
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR5
Pin Control Register n
0x3C
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR6
Pin Control Register n
0x54
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR7
Pin Control Register n
0x70
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PORTB
Pin Control and Interrupts
PORT
0x0
0x0
0xA4
registers
n
PTx
17
GPCHR
Global Pin Control High Register
0x84
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCLR
Global Pin Control Low Register
0x80
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
n
0x0
0x0
ISF
Interrupt Status Flag
0
32
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR0
Pin Control Register n
0x0
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR1
Pin Control Register n
0x4
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR2
Pin Control Register n
0xC
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR3
Pin Control Register n
0x18
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR4
Pin Control Register n
0x28
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR5
Pin Control Register n
0x3C
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR6
Pin Control Register n
0x54
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR7
Pin Control Register n
0x70
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PORTC
Pin Control and Interrupts
PORT
0x0
0x0
0xA4
registers
n
PTx
17
GPCHR
Global Pin Control High Register
0x84
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCLR
Global Pin Control Low Register
0x80
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
n
0x0
0x0
ISF
Interrupt Status Flag
0
32
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR0
Pin Control Register n
0x0
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR1
Pin Control Register n
0x4
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR2
Pin Control Register n
0xC
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR3
Pin Control Register n
0x18
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR4
Pin Control Register n
0x28
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR5
Pin Control Register n
0x3C
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR6
Pin Control Register n
0x54
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR7
Pin Control Register n
0x70
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PORTD
Pin Control and Interrupts
PORT
0x0
0x0
0xA4
registers
n
PTx
17
GPCHR
Global Pin Control High Register
0x84
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCLR
Global Pin Control Low Register
0x80
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
n
0x0
0x0
ISF
Interrupt Status Flag
0
32
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR0
Pin Control Register n
0x0
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR1
Pin Control Register n
0x4
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR2
Pin Control Register n
0xC
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR3
Pin Control Register n
0x18
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR4
Pin Control Register n
0x28
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR5
Pin Control Register n
0x3C
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR6
Pin Control Register n
0x54
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR7
Pin Control Register n
0x70
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PORTE
Pin Control and Interrupts
PORT
0x0
0x0
0xCC
registers
n
PTx
17
DFCR
Digital Filter Clock Register
0xC4
32
read-write
n
0x0
0x0
CS
Clock Source
0
1
read-write
0
Digital filters are clocked by the bus clock.
#0
1
Digital filters are clocked by the 1 kHz LPO clock.
#1
DFER
Digital Filter Enable Register
0xC0
32
read-write
n
0x0
0x0
DFE
Digital Filter Enable
0
32
read-write
0
Digital filter is disabled on the corresponding pin and output of the digital filter is reset to zero.
#0
1
Digital filter is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
DFWR
Digital Filter Width Register
0xC8
32
read-write
n
0x0
0x0
FILT
Filter Length
0
5
read-write
GPCHR
Global Pin Control High Register
0x84
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCLR
Global Pin Control Low Register
0x80
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
n
0x0
0x0
ISF
Interrupt Status Flag
0
32
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR0
Pin Control Register n
0x0
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR1
Pin Control Register n
0x4
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR2
Pin Control Register n
0xC
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR3
Pin Control Register n
0x18
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR4
Pin Control Register n
0x28
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR5
Pin Control Register n
0x3C
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR6
Pin Control Register n
0x54
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR7
Pin Control Register n
0x70
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PORTF
Pin Control and Interrupts
PORT
0x0
0x0
0xA4
registers
n
PTx
17
GPCHR
Global Pin Control High Register
0x84
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCLR
Global Pin Control Low Register
0x80
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
n
0x0
0x0
ISF
Interrupt Status Flag
0
32
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR0
Pin Control Register n
0x0
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR1
Pin Control Register n
0x4
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR2
Pin Control Register n
0xC
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR3
Pin Control Register n
0x18
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR4
Pin Control Register n
0x28
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR5
Pin Control Register n
0x3C
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR6
Pin Control Register n
0x54
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR7
Pin Control Register n
0x70
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PORTG
Pin Control and Interrupts
PORT
0x0
0x0
0xA4
registers
n
PTx
17
GPCHR
Global Pin Control High Register
0x84
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCLR
Global Pin Control Low Register
0x80
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
n
0x0
0x0
ISF
Interrupt Status Flag
0
32
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR0
Pin Control Register n
0x0
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR1
Pin Control Register n
0x4
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR2
Pin Control Register n
0xC
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR3
Pin Control Register n
0x18
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR4
Pin Control Register n
0x28
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR5
Pin Control Register n
0x3C
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR6
Pin Control Register n
0x54
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR7
Pin Control Register n
0x70
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PORTH
Pin Control and Interrupts
PORT
0x0
0x0
0xA4
registers
n
PTx
17
GPCHR
Global Pin Control High Register
0x84
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCLR
Global Pin Control Low Register
0x80
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
n
0x0
0x0
ISF
Interrupt Status Flag
0
32
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR0
Pin Control Register n
0x0
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR1
Pin Control Register n
0x4
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR2
Pin Control Register n
0xC
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR3
Pin Control Register n
0x18
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR4
Pin Control Register n
0x28
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR5
Pin Control Register n
0x3C
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR6
Pin Control Register n
0x54
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR7
Pin Control Register n
0x70
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PORTI
Pin Control and Interrupts
PORT
0x0
0x0
0xA4
registers
n
PTx
17
GPCHR
Global Pin Control High Register
0x84
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
GPCLR
Global Pin Control Low Register
0x80
32
write-only
n
0x0
0x0
GPWD
Global Pin Write Data
0
16
write-only
GPWE
Global Pin Write Enable
16
16
write-only
0
Corresponding Pin Control Register is not updated with the value in GPWD.
#0
1
Corresponding Pin Control Register is updated with the value in GPWD.
#1
ISFR
Interrupt Status Flag Register
0xA0
32
read-write
n
0x0
0x0
ISF
Interrupt Status Flag
0
32
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
PCR0
Pin Control Register n
0x0
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR1
Pin Control Register n
0x4
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR2
Pin Control Register n
0xC
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR3
Pin Control Register n
0x18
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR4
Pin Control Register n
0x28
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR5
Pin Control Register n
0x3C
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR6
Pin Control Register n
0x54
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
PCR7
Pin Control Register n
0x70
32
read-write
n
0x0
0x0
IRQC
Interrupt Configuration
16
4
read-write
0000
Interrupt/DMA request disabled.
#0000
0001
DMA request on rising edge.
#0001
0010
DMA request on falling edge.
#0010
0011
DMA request on either edge.
#0011
1000
Interrupt when logic zero.
#1000
1001
Interrupt on rising edge.
#1001
1010
Interrupt on falling edge.
#1010
1011
Interrupt on either edge.
#1011
1100
Interrupt when logic one.
#1100
ISF
Interrupt Status Flag
24
1
read-write
0
Configured interrupt is not detected.
#0
1
Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic one is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared.
#1
LK
Lock Register
15
1
read-write
0
Pin Control Register fields [15:0] are not locked.
#0
1
Pin Control Register fields [15:0] are locked and cannot be updated until the next system reset.
#1
MUX
Pin Mux Control
8
3
read-write
000
Pin disabled (analog).
#000
001
Alternative 1 (GPIO).
#001
010
Alternative 2 (chip-specific).
#010
011
Alternative 3 (chip-specific).
#011
100
Alternative 4 (chip-specific).
#100
101
Alternative 5 (chip-specific).
#101
110
Alternative 6 (chip-specific).
#110
111
Alternative 7 (chip-specific).
#111
PE
Pull Enable
1
1
read-write
0
Internal pullup or pulldown resistor is not enabled on the corresponding pin.
#0
1
Internal pullup or pulldown resistor is enabled on the corresponding pin, if the pin is configured as a digital input.
#1
PS
Pull Select
0
1
read-write
0
Internal pulldown resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#0
1
Internal pullup resistor is enabled on the corresponding pin, if the corresponding Port Pull Enable field is set.
#1
SRE
Slew Rate Enable
2
1
read-write
0
Fast slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#0
1
Slow slew rate is configured on the corresponding pin, if the pin is configured as a digital output.
#1
RCM
Reset Control Module
RCM
0x0
0x0
0x6
registers
n
RPFC
Reset Pin Filter Control register
0x4
8
read-write
n
0x0
0x0
RSTFLTSRW
Reset Pin Filter Select in Run and Wait Modes
0
2
read-write
00
All filtering disabled
#00
01
Bus clock filter enabled for normal operation
#01
10
LPO clock filter enabled for normal operation
#10
RSTFLTSS
Reset Pin Filter Select in Stop Mode
2
1
read-write
0
All filtering disabled
#0
1
LPO clock filter enabled
#1
RPFW
Reset Pin Filter Width register
0x5
8
read-write
n
0x0
0x0
RSTFLTSEL
Reset Pin Filter Bus Clock Select
0
5
read-write
00000
Bus clock filter count is 1
#00000
00001
Bus clock filter count is 2
#00001
00010
Bus clock filter count is 3
#00010
00011
Bus clock filter count is 4
#00011
00100
Bus clock filter count is 5
#00100
00101
Bus clock filter count is 6
#00101
00110
Bus clock filter count is 7
#00110
00111
Bus clock filter count is 8
#00111
01000
Bus clock filter count is 9
#01000
01001
Bus clock filter count is 10
#01001
01010
Bus clock filter count is 11
#01010
01011
Bus clock filter count is 12
#01011
01100
Bus clock filter count is 13
#01100
01101
Bus clock filter count is 14
#01101
01110
Bus clock filter count is 15
#01110
01111
Bus clock filter count is 16
#01111
10000
Bus clock filter count is 17
#10000
10001
Bus clock filter count is 18
#10001
10010
Bus clock filter count is 19
#10010
10011
Bus clock filter count is 20
#10011
10100
Bus clock filter count is 21
#10100
10101
Bus clock filter count is 22
#10101
10110
Bus clock filter count is 23
#10110
10111
Bus clock filter count is 24
#10111
11000
Bus clock filter count is 25
#11000
11001
Bus clock filter count is 26
#11001
11010
Bus clock filter count is 27
#11010
11011
Bus clock filter count is 28
#11011
11100
Bus clock filter count is 29
#11100
11101
Bus clock filter count is 30
#11101
11110
Bus clock filter count is 31
#11110
11111
Bus clock filter count is 32
#11111
SRS0
System Reset Status Register 0
0x0
8
read-only
n
0x0
0x0
LOC
Loss-of-Clock Reset
2
1
read-only
0
Reset not caused by a loss of external clock.
#0
1
Reset caused by a loss of external clock.
#1
LOL
Loss-of-Lock Reset
3
1
read-only
0
Reset not caused by a loss of lock in the PLL
#0
1
Reset caused by a loss of lock in the PLL
#1
LVD
Low-Voltage Detect Reset
1
1
read-only
0
Reset not caused by LVD trip or POR
#0
1
Reset caused by LVD trip or POR
#1
PIN
External Reset Pin
6
1
read-only
0
Reset not caused by external reset pin
#0
1
Reset caused by external reset pin
#1
POR
Power-On Reset
7
1
read-only
0
Reset not caused by POR
#0
1
Reset caused by POR
#1
WAKEUP
Low Leakage Wakeup Reset
0
1
read-only
0
Reset not caused by wakeup source
#0
1
Reset caused by wakeup source
#1
WDOG
Watchdog
5
1
read-only
0
Reset not caused by watchdog timeout
#0
1
Reset caused by watchdog timeout
#1
SRS1
System Reset Status Register 1
0x1
8
read-only
n
0x0
0x0
LOCKUP
Core Lockup
1
1
read-only
0
Reset not caused by core LOCKUP event
#0
1
Reset caused by core LOCKUP event
#1
MDM_AP
MDM-AP System Reset Request
3
1
read-only
0
Reset not caused by host debugger system setting of the System Reset Request bit
#0
1
Reset caused by host debugger system setting of the System Reset Request bit
#1
SACKERR
Stop Mode Acknowledge Error Reset
5
1
read-only
0
Reset not caused by peripheral failure to acknowledge attempt to enter stop mode
#0
1
Reset caused by peripheral failure to acknowledge attempt to enter stop mode
#1
SW
Software
2
1
read-only
0
Reset not caused by software setting of SYSRESETREQ bit
#0
1
Reset caused by software setting of SYSRESETREQ bit
#1
RNG
Random Number Generator Accelerator
RNG
0x0
0x0
0x10
registers
n
CR
RNGA Control Register
0x0
32
read-write
n
0x0
0x0
CLRI
Clear Interrupt
3
1
write-only
0
Do not clear the interrupt.
#0
1
Clear the interrupt. When you write 1 to this field, RNGA then resets the error-interrupt indicator (SR[ERRI]). This bit always reads as 0.
#1
GO
Go
0
1
read-write
0
Disabled
#0
1
Enabled
#1
HA
High Assurance
1
1
read-write
0
Disabled
#0
1
Enabled
#1
INTM
Interrupt Mask
2
1
read-write
0
Not masked
#0
1
Masked
#1
SLP
Sleep
4
1
read-write
0
Normal mode
#0
1
Sleep (low-power) mode
#1
ER
RNGA Entropy Register
0x8
32
write-only
n
0x0
0x0
EXT_ENT
External Entropy
0
32
write-only
OR
RNGA Output Register
0xC
32
read-only
n
0x0
0x0
RANDOUT
Random Output
0
32
read-only
0
Invalid data (if you read this field when it is 0 and SR[OREG_LVL] is 0, RNGA then writes 1 to SR[ERRI], SR[ORU], and SR[LRS]; when the error interrupt is not masked (CR[INTM]=0), RNGA also asserts an error interrupt request to the interrupt controller).
#0
SR
RNGA Status Register
0x4
32
read-only
n
0x0
0x0
ERRI
Error Interrupt
3
1
read-only
0
No underflow
#0
1
Underflow
#1
LRS
Last Read Status
1
1
read-only
0
No underflow
#0
1
Underflow
#1
OREG_LVL
Output Register Level
8
8
read-only
0
No words (empty)
#0
1
One word (valid)
#1
OREG_SIZE
Output Register Size
16
8
read-only
1
One word (this value is fixed)
#1
ORU
Output Register Underflow
2
1
read-only
0
No underflow
#0
1
Underflow
#1
SECV
Security Violation
0
1
read-only
0
No security violation
#0
1
Security violation
#1
SLP
Sleep
4
1
read-only
0
Normal mode
#0
1
Sleep (low-power) mode
#1
ROM
System ROM
ROM
0x0
0x0
0x1000
registers
n
COMPID0
Component ID Register
0x1FE0
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID1
Component ID Register
0x2FD4
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID2
Component ID Register
0x3FCC
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
COMPID3
Component ID Register
0x4FC8
32
read-only
n
0x0
0x0
COMPID
Component ID
0
32
read-only
ENTRY0
Entry
0x0
32
read-only
n
0x0
0x0
ENTRY
ENTRY
0
32
read-only
ENTRY1
Entry
0x4
32
read-only
n
0x0
0x0
ENTRY
ENTRY
0
32
read-only
ENTRY2
Entry
0xC
32
read-only
n
0x0
0x0
ENTRY
ENTRY
0
32
read-only
PERIPHID0
Peripheral ID Register
0x5F08
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID1
Peripheral ID Register
0x6EEC
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID2
Peripheral ID Register
0x7ED4
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID3
Peripheral ID Register
0x8EC0
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID4
Peripheral ID Register
0x1FA0
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID5
Peripheral ID Register
0x2F74
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID6
Peripheral ID Register
0x3F4C
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
PERIPHID7
Peripheral ID Register
0x4F28
32
read-only
n
0x0
0x0
PERIPHID
PERIPHID
0
32
read-only
SYSACCESS
System Access Register
0xFCC
32
read-only
n
0x0
0x0
SYSACCESS
SYSACCESS
0
32
read-only
TABLEMARK
End of Table Marker Register
0xC
32
read-only
n
0x0
0x0
MARK
MARK
0
32
read-only
RTC
Real Time Clock
RTC
0x0
0x0
0x44
registers
n
RTC
25
ALM_DAYS
RTC Days Alarm Register
0xA
16
read-write
n
0x0
0x0
ALM_DAY
Days Value for Alarm.
0
5
read-write
ALM_HOURMIN
RTC Hours and Minutes Alarm Register
0xC
16
read-write
n
0x0
0x0
ALM_HOUR
Hours Value for Alarm.
8
5
read-write
ALM_MIN
Minutes Value for Alarm.
0
6
read-write
ALM_SECONDS
RTC Seconds Alarm Register
0xE
16
read-write
n
0x0
0x0
ALM_SEC
no description available
0
6
read-write
DEC_SEC
Decrement Seconds Counter by 1.
8
1
write-only
INC_SEC
Increment Seconds Counter by 1.
9
1
write-only
ALM_YEARMON
RTC Year and Months Alarm Register
0x8
16
read-write
n
0x0
0x0
ALM_MON
Months Value for Alarm.
0
4
read-write
ALM_YEAR
Year Value for Alarm.
8
8
read-write
COMPEN
RTC Compensation Register
0x28
16
read-write
n
0x0
0x0
COMPEN_VAL
Compensation Value
0
16
read-write
CTRL
RTC Control Register
0x10
16
read-write
n
0x0
0x0
ALM_MATCH
Alarm Match bits.
2
2
read-write
00
Only Seconds, Minutes, and Hours matched.
#00
01
Only Seconds, Minutes, Hours, and Days matched.
#01
10
Only Seconds, Minutes, Hours, Days, and Months matched.
#10
CLKOUT
RTC Clock Output Selection.
13
2
read-write
00
No Output Clock
#00
01
Fine 1 Hz Clock
#01
10
32.768 kHz Clock
#10
11
Coarse 1 Hz Clock
#11
COMP_EN
no description available
1
1
read-write
DST_EN
Daylight Saving Enable.
6
1
read-write
0
Disabled. Daylight saving changes are not applied. Daylight saving registers can be modified.
#0
1
Enabled. Daylight saving changes are applied.
#1
FINEEN
Fine compensation enable bit
0
1
read-write
0
Fine compensation is disabled
#0
1
Fine compensation is enabled.
#1
SWR
Software Reset bit.
8
1
write-only
0
Software Reset cleared.
#0
1
Software Reset asserted.
#1
TIMER_STB_MASK
Sampling timer clocks mask
4
1
read-write
0
Sampling clocks are not gated when in standby mode
#0
1
Sampling clocks are gated in standby mode
#1
CTRL2
RTC Control 2 Register
0x42
16
read-write
n
0x0
0x0
TAMP_CFG_OVER
Tamper Configuration Over
0
1
read-write
0
Tamper filter processing disabled.
#0
1
Tamper filter processing enabled.
#1
WAKEUP_MODE
Wakeup Mode
7
1
read-write
0
Tamper pin 0 is used as the tamper pin.
#0
1
Tamper pin 0 is used as a wakeup/hibernation pin.
#1
WAKEUP_STATUS
Wakeup Status
5
2
read-write
00
The wakeup/hibernation pin is in HiZ mode.
#00
01
The wakeup/hibernation pin is at logic 0. MCU is in sleep mode.
#01
10
The wakeup/ hibernation pin is at logic 1. MCU is in sleep mode.
#10
DAYS
RTC Days and Day-of-Week Counters Register
0x2
16
read-write
n
0x0
0x0
DAY_CNT
Days Counter Value.
0
5
read-write
DOW
Day of Week Counter Value.
8
3
read-write
0
Sunday
#0
1
Monday
#1
DST_DAY
RTC Daylight Saving Day Register
0x26
16
read-write
n
0x0
0x0
DST_END_DAY
Daylight Saving Time (DST) Day End Value.
0
5
read-write
DST_START_DAY
Daylight Saving Time (DST) Day Start Value.
8
5
read-write
DST_HOUR
RTC Daylight Saving Hour Register
0x22
16
read-write
n
0x0
0x0
DST_END_HOUR
Daylight Saving Time (DST) Hours End Value.
0
5
read-write
DST_START_HOUR
Daylight Saving Time (DST) Hours Start Value.
8
5
read-write
DST_MONTH
RTC Daylight Saving Month Register
0x24
16
read-write
n
0x0
0x0
DST_END_MONTH
Daylight Saving Time (DST) Month End Value.
0
4
read-write
DST_START_MONTH
Daylight Saving Time (DST) Month Start Value.
8
4
read-write
FILTER01_CFG
RTC Tamper 0 1 Filter Configuration Register
0x34
16
read-write
n
0x0
0x0
CLK_SEL0
Tamper Filter 0 Clock Select
12
3
read-write
000
32 kHz clock
#000
001
512 Hz clock
#001
010
128 Hz clock
#010
011
64 Hz clock
#011
100
16 Hz clock
#100
101
8 Hz clock
#101
110
4 Hz clock
#110
111
2 Hz clock
#111
CLK_SEL1
Tamper Filter 1 Clock Select
4
3
read-write
000
32 kHz clock
#000
001
512 Hz clock
#001
010
128 Hz clock
#010
011
64 Hz clock
#011
100
16 Hz clock
#100
101
8 Hz clock
#101
110
4 Hz clock
#110
111
2 Hz clock
#111
FIL_DUR0
Tamper Detect Bit 0 Filter Duration
8
4
read-write
0
Filtering operation disabled.
#0
FIL_DUR1
Tamper Detect Bit 1 Filter Duration
0
4
read-write
0
Filtering operation disabled.
#0
POL0
Tamper Detect Input Bit 0 Polarity Control
15
1
read-write
0
Tamper detect input bit 0 is active high.
#0
1
Tamper detect input bit 0 is active low.
#1
POL1
Tamper Detect Input Bit 1 Polarity Control
7
1
read-write
0
Tamper detect input bit 1 is active high.
#0
1
Tamper detect input bit 1 is active low.
#1
FILTER2_CFG
RTC Tamper 2 Filter Configuration Register
0x36
16
read-write
n
0x0
0x0
CLK_SEL2
Tamper Filter 2 Clock Select
12
3
read-write
000
32 kHz clock
#000
001
512 Hz clock
#001
010
128 Hz clock
#010
011
64 Hz clock
#011
100
16 Hz clock
#100
101
8 Hz clock
#101
110
4 Hz clock
#110
111
2 Hz clock
#111
FIL_DUR2
Tamper Detect Bit 2 Filter Duration
8
4
read-write
0
Filtering operation disabled.
#0
POL2
Tamper Detect Input Bit 2 Polarity Control
15
1
read-write
0
Tamper detect input bit 2 is active high.
#0
1
Tamper detect input bit 2 is active low.
#1
GP_DATA_REG
RTC General Purpose Data Register
0x20
16
read-write
n
0x0
0x0
GP_DATA_REG
no description available
0
16
read-write
HOURMIN
RTC Hours and Minutes Counters Register
0x4
16
read-write
n
0x0
0x0
HOUR_CNT
Hours Counter Value.
8
5
read-write
MIN_CNT
Minutes Counter Value.
0
6
read-write
IER
RTC Interrupt Enable Register
0x16
16
read-write
n
0x0
0x0
ALM_IE
Alarm Interrupt Enable bit.
2
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
DAY_IE
Days Interrupt Enable bit.
3
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
HOUR_IE
Hours Interrupt Enable bit.
4
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
IE_128HZ
128 Hz Interval Interrupt Enable bit.
13
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
IE_16HZ
16 Hz Interval Interrupt Enable bit.
10
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
IE_1HZ
1 Hz Interval Interrupt Enable bit.
6
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
IE_256HZ
256 Hz Interval Interrupt Enable bit.
14
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
IE_2HZ
2 Hz Interval Interrupt Enable bit.
7
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
IE_32HZ
32 Hz Interval Interrupt Enable bit.
11
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
IE_4HZ
4 Hz Interval Interrupt Enable bit.
8
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
IE_512HZ
512 Hz Interval Interrupt Enable bit.
15
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
IE_64HZ
64 Hz Interval Interrupt Enable bit.
12
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
IE_8HZ
8 Hz Interval Interrupt Enable bit.
9
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
MIN_IE
Minutes Interrupt Enable bit.
5
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled.
#1
TAMPER_IE
Tamper Interrupt Enable bit.
0
1
read-write
0
Interrupt is disabled.
#0
1
Interrupt is enabled (Default on reset).
#1
ISR
RTC Interrupt Status Register
0x14
16
read-write
n
0x0
0x0
ALM_IS
Alarm Interrupt Status bit.
2
1
read-write
0
Interrupt is de-asserted.
#0
1
Interrupt is asserted.
#1
DAY_IS
Days Interrupt Status bit.
3
1
read-write
0
Interrupt is de-asserted.
#0
1
Interrupt is asserted.
#1
HOUR_IS
Hours Interrupt Status bit.
4
1
read-write
0
Interrupt is de-asserted.
#0
1
Interrupt is asserted.
#1
IS_128HZ
128 Hz Interval Interrupt Status bit.
13
1
read-write
0
Interrupt is de-asserted.
#0
1
Interrupt is asserted.
#1
IS_16HZ
16 Hz Interval Interrupt Status bit.
10
1
read-write
0
Interrupt is de-asserted.
#0
1
Interrupt is asserted.
#1
IS_1HZ
1 Hz Interval Interrupt Status bit.
6
1
read-write
0
Interrupt is de-asserted.
#0
1
Interrupt is asserted.
#1
IS_256HZ
256 Hz Interval Interrupt Status bit.
14
1
read-write
0
Interrupt is de-asserted.
#0
1
Interrupt is asserted.
#1
IS_2HZ
2 Hz Interval Interrupt Status bit.
7
1
read-write
0
Interrupt is de-asserted.
#0
1
Interrupt is asserted.
#1
IS_32HZ
32 Hz Interval Interrupt Status bit.
11
1
read-write
0
Interrupt is de-asserted.
#0
1
Interrupt is asserted.
#1
IS_4HZ
4 Hz Interval Interrupt Status bit.
8
1
read-write
0
Interrupt is de-asserted.
#0
1
Interrupt is asserted.
#1
IS_512HZ
512 Hz Interval Interrupt Status bit.
15
1
read-write
0
Interrupt is de-asserted.
#0
1
Interrupt is asserted.
#1
IS_64HZ
64 Hz Interval Interrupt Status bit.
12
1
read-write
0
Interrupt is de-asserted.
#0
1
Interrupt is asserted.
#1
IS_8HZ
8 Hz Interval Interrupt Status bit.
9
1
read-write
0
Interrupt is de-asserted.
#0
1
Interrupt is asserted.
#1
MIN_IS
Minutes Interrupt Status bit.
5
1
read-write
0
Interrupt is de-asserted.
#0
1
Interrupt is asserted.
#1
TAMPER_IS
Tamper Interrupt Status bit.
0
1
read-only
0
Interrupt is de-asserted.
#0
1
Interrupt is asserted (Default on reset) .
#1
SECONDS
RTC Seconds Counters Register
0x6
16
read-write
n
0x0
0x0
SEC_CNT
Seconds Counter Value.
0
6
read-write
STATUS
RTC Status Register
0x12
16
read-write
n
0x0
0x0
BUS_ERR
Bus Error bit.
8
1
read-write
0
Read and Write accesses are normal.
#0
1
Read or Write accesses occurred when INVAL_BIT was asserted.
#1
CMP_DONE
Compensation Done bit.
11
1
read-write
0
Compensation busy or not enabled.
#0
1
Compensation completed.
#1
CMP_INT
Compensation Interval bit.
5
1
read-only
CPU_LOW_VOLT
CPU Low Voltage Warning status bit.
2
1
read-only
0
CPU in Normal Operating Voltage.
#0
1
CPU Voltage is below Normal Operating Voltage. RTC Registers in read-only mode.
#1
INVAL_BIT
Invalidate CPU read/write access bit.
0
1
read-only
0
Time /Date Counters can be read/written. Time /Date is valid.
#0
1
Time /Date Counter values are changing or Time /Date is invalid and cannot be read or written.
#1
RST_SRC
Reset Source bit.
3
1
read-only
0
Part was reset due to Standby Mode Exit (that is when VDD is powered up and VBAT was not powered down at all).
#0
1
Part was reset due to Power-On Reset (that is Power On Reset when both VBAT and VDD are powered up).
#1
WE
Write Enable bits.
6
2
write-only
10
Enable Write Protection - Registers are locked.
#10
WRITE_PROT_EN
Write Protect Enable status bit.
1
1
read-only
0
Registers are unlocked and can be accessed.
#0
1
Registers are locked and in read-only mode.
#1
TAMPER_DIRECTION
Tamper Direction Register
0x2C
16
read-write
n
0x0
0x0
A_P_TAMP
no description available
0
4
read-write
I_O_TAMP
no description available
8
4
read-write
TAMPER_QSCR
Tamper Queue Status and Control Register
0x2E
16
read-write
n
0x0
0x0
LFSR_CLK_SEL
no description available
8
3
read-write
LFSR_DURATION
no description available
12
4
read-write
Q_CLEAR
no description available
2
1
write-only
Q_FULL
no description available
0
1
read-write
Q_FULL_INT_EN
no description available
1
1
read-write
TAMPER_QUEUE
Tamper Queue Register
0x40
16
read-only
n
0x0
0x0
TAMPER_DATA
Tamper type stamp and pin number information register
0
16
read-only
TAMPER_SCR
RTC Tamper Status and Control Register
0x32
16
read-write
n
0x0
0x0
TMPR_EN
Tamper Control
0
4
read-write
TMPR_STS
Tamper Status Bit
8
4
read-write
YEARMON
RTC Year and Month Counters Register
0x0
16
read-write
n
0x0
0x0
MON_CNT
no description available
0
4
read-write
0
Illegal Value
#0
1
January
#1
10
October
#10
11
November
#11
YROFST
Year Offset Count Value
8
8
read-write
SIM
System Integration Module
SIM
0x0
0x0
0x1070
registers
n
CLKDIV1
System Clock Divider Register 1
0x1044
32
read-write
n
0x0
0x0
SYSCLKMODE
System Clock Mode
27
1
read-write
0
1:1:1
#0
1
2:1:1
#1
SYSDIV
System Clock divider
28
4
read-write
0000
Divide by 1
#0000
0001
Divide by 2
#0001
0010
Divide by 3
#0010
0011
Divide by 4 and so on..... If FOPT[0] is 0, the divider is set to div-by-8 after system reset is deasserted (after completion of system initialization sequence)
#0011
CTRL_REG
System Control Register
0x1004
32
read-write
n
0x0
0x0
CLKOUTSEL
Clock out Select
5
3
read-write
000
Disabled
#000
001
Gated Core Clk
#001
010
Bus/Flash Clk
#010
011
LPO clock from PMC
#011
100
IRC clock from MCG
#100
101
Muxed 32Khz source (please refer SOPT1[19:18] for possible options)
#101
110
MHz Oscillator external reference clock
#110
111
PLL clock output from MCG
#111
NMIDIS
NMI Disable
0
1
read-write
0
NMI enabled
#0
1
NMI disabled
#1
PLL_VLP_EN
PLL VLP Enable
1
1
read-write
PTC2_HD_EN
PTC2 HighDrive Enable
2
1
read-write
SAR_TRG_CLK_SEL
SAR ADC Trigger Clk Select
3
2
read-write
00
Bus Clock (During Low Power Modes such as stop, the Bus clock is not available for conversion and should not be selected in case a conversion needs to be performed while in stop)
#00
01
ADC asynchronous Clock
#01
10
ERCLK32K
#10
11
OSCCLK
#11
FCFG1
Flash Configuration Register 1
0x104C
32
read-write
n
0x0
0x0
FLASHDIS
Flash Disable
0
1
read-write
0
Flash is enabled
#0
1
Flash is disabled
#1
FLASHDOZE
Flash Doze
1
1
read-write
0
Flash remains enabled during Wait mode
#0
1
Flash is disabled for the duration of Wait mode
#1
PFSIZE
Program flash size
24
4
read-only
0101
64 KB of program flash memory, 2 KB protection region
#0101
0111
128 KB of program flash memory, 4 KB protection region
#0111
1111
(Default)
#1111
FCFG2
Flash Configuration Register 2
0x1050
32
read-only
n
0x0
0x0
MAXADDR
Max address block
24
7
read-only
MISC_CTL
Miscellaneous Control Register
0x106C
32
read-write
n
0x0
0x0
AFECLKPADDIR
AFE Clock Pad Direction
6
1
read-write
0
AFE CLK PAD is input
#0
1
AFE CLK PAD is output
#1
AFECLKSEL
AFE Clock Source Select
4
2
read-write
00
MCG PLL Clock selected
#00
01
MCG FLL Clock selected
#01
10
OSC Clock selected
#10
11
Disabled
#11
DMADONESEL
DMA Done select
2
2
read-write
00
DMA0
#00
01
DMA1
#01
10
DMA2
#10
11
DMA3
#11
EWMINSEL
External Watchdog Monitor Input Select
14
1
read-write
0
Input from PAD (PTE[2] or PTE[4] as selected from Pinmux control )
#0
1
Peripheral Crossbar (XBAR) Output[32]
#1
RTCCLKSEL
RTC Clock select
28
1
read-write
0
RTC OSC_32K clock selected
#0
1
32K IRC Clock selected
#1
TMR0PCSSEL
Quadtimer Channel0 Primary Count Source Select
20
2
read-write
00
Bus Clock
#00
01
Peripheral Crossbar Output [9]
#01
10
Peripheral Crossbar Output [10]
#10
11
Disabled
#11
TMR0PLLCLKSEL
Timer CH0 PLL clock select
15
1
read-write
0
Selects Bus Clock as source for the Timer CH0
#0
1
Selects the PLL_AFE clock as the source for Timer CH0. The PLL_AFE clock source is itself selected using the MISC_CTL[5:4]
#1
TMR0SCSSEL
Quadtimer Channel0 Secondary Count Source Select
16
1
read-write
0
Pad PTF1 or PTD5, depending upon PCTL configuration.
#0
1
Peripheral Crossbar (XBAR) Output[5]
#1
TMR1PCSSEL
Quadtimer Channel1 Primary Count Source Select
22
2
read-write
00
Bus Clock
#00
01
Peripheral Crossbar Output [9]
#01
10
Peripheral Crossbar Output [10]
#10
11
Disabled
#11
TMR1SCSSEL
Quadtimer Channel1 Secondary Count Source Select
17
1
read-write
0
Pad PTG0 or PTC6, depending upon PCTL configuration.
#0
1
Peripheral Crossbar (XBAR) Output[6]
#1
TMR2PCSSEL
Quadtimer Channel2 Primary Count Source Select
24
2
read-write
00
Bus Clock
#00
01
Peripheral Crossbar Output [9]
#01
10
Peripheral Crossbar Output [10]
#10
11
Disabled
#11
TMR2SCSSEL
Quadtimer Channel2 Secondary Count Source Select
18
1
read-write
0
Pad PTF7 or PTF0, depending upon PCTL configuration.
#0
1
Peripheral Crossbar (XBAR) Output[7]
#1
TMR3PCSSEL
Quadtimer Channel3 Primary Count Source Select
26
2
read-write
00
Bus Clock
#00
01
Peripheral Crossbar Output [9]
#01
10
Peripheral Crossbar Output [10]
#10
11
Disabled
#11
TMR3SCSSEL
Quadtimer Channel3 Secondary Count Source Select
19
1
read-write
0
Pad PTE5 or PTD1, depending upon PCTL configuration.
#0
1
Peripheral Crossbar (XBAR) Output[8]
#1
UART0IRSEL
UART0 IRDA Select
8
1
read-write
0
Pad RX input (PTD[0] or PTF[3], as selected in Pinmux control) selected for RX input of UART0 and UART0 TX signal is not used for modulation
#0
1
UART0 selected for IRDA modulation. UART0 TX modulated by XBAR_OUT[14] and UART0 RX input connected to XBAR_OUT[13]
#1
UART1IRSEL
UART1 IRDA Select
9
1
read-write
0
Pad RX input (PTD[2] or PTI[0], as selected in Pinmux control) selected for RX input of UART1 and UART1 TX signal is not used for modulation
#0
1
UART1 selected for IRDA modulation. UART1 TX modulated by XBAR_OUT[14] and UART1 RX input connected to XBAR_OUT[13]
#1
UART2IRSEL
UART2 IRDA Select
10
1
read-write
0
Pad RX input PTE[6] selected for RX input of UART2 and UART2 TX signal is not used for modulation
#0
1
UART2 selected for IRDA modulation. UART2 TX modulated by XBAR_OUT[14] and UART2 RX input connected to XBAR_OUT[13].
#1
UART3IRSEL
UART3 IRDA Select
11
1
read-write
0
Pad RX input (PTC[3] or PTD[7], as selected in Pinmux control) selected for RX input of UART3 and UART3 TX signal is not used for modulation
#0
1
UART3 selected for IRDA modulation. UART3 TX modulated by XBAR_OUT[14] and UART3 RX input connected to XBAR_OUT[13].
#1
UARTMODTYPE
UART Modulation Type
7
1
read-write
0
TypeA (ORed) Modulation selected for IRDA
#0
1
TypeB (ANDed) Modulation selected for IRDA
#1
VREFBUFINSEL
VrefBuffer Input Select
30
1
read-write
0
Internal Reference selected as Buffer Input
#0
1
External Reference selected as Buffer Input
#1
VREFBUFOUTEN
VrefBuffer Output Enable
29
1
read-write
0
Buffer does not drive PAD
#0
1
Buffer drives selected voltage (selected by vref_buffer_sel) on pad
#1
VREFBUFPD
VrefBuffer Power Down
31
1
read-write
0
Buffer Enabled
#0
1
Buffer Powered Down
#1
XBARAFEMODOUTSEL
XBAR AFE Modulator Output Select
0
2
read-write
00
Sigma Delta Modulator 0 data output
#00
01
Sigma Delta Modulator 1 data output
#01
10
Sigma Delta Modulator 2 data output
#10
11
Sigma Delta Modulator 3 data output
#11
XBARPITOUTSEL
XBAR PIT Output select
12
2
read-write
00
PIT0[0] (default)
#00
01
PIT0[1]
#01
10
PIT1[0]
#10
11
PIT1[1]
#11
SCGC4
System Clock Gating Control Register 4
0x1034
32
read-write
n
0x0
0x0
CMP0
High Speed Comparator0 Clock Gate Control.
18
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
CMP1
High Speed Comparator1 Clock Gate Control.
19
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
EWM
External Watchdog Monitor Clock gate control
1
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
I2C0
I2C0 Clock Gate Control
7
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
I2C1
I2C1 Clock Gate Control
8
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
MCG
MCG clock gate control.
4
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
OSC
Oscillator (Mhz) Clock Gate Control
6
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SPI0
SPI0 Clock Gate Control
21
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SPI1
SPI1 Clock Gate Control
22
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
UART0
UART0 Clock Gate Control
10
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
UART1
UART1 Clock Gate Control
11
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
UART2
UART2 Clock Gate Control
12
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
UART3
UART3 Clock Gate Control
13
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
VREF
VREF Clock Gate Control
15
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SCGC5
System Clock Gating Control Register 5
0x1038
32
read-write
n
0x0
0x0
IRTC
IRTC Clock Gate Control
16
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
IRTCREGFILE
IRTC_REG_FILE Clock Gate Control
17
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTA
PCTLA Clock Gate Control
6
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTB
PCTLB Clock Gate Control
7
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTC
PCTLC Clock Gate Control
8
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTD
PCTLD Clock Gate Control
9
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTE
PCTLE Clock Gate Control
10
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTF
PCTLF Clock Gate Control
11
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTG
PCTLG Clock Gate Control
12
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTH
PCTLH Clock Gate Control
13
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PORTI
PCTLI Clock Gate Control
14
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SLCD
Segmented LCD Clock Gate Control
3
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
TMR0
Quadtimer0 Clock Gate Control
23
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
TMR1
Quadtimer1 Clock Gate Control
24
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
TMR2
Quadtimer2 Clock Gate Control
25
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
TMR3
Quadtimer3 Clock Gate Control
26
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
WDOG
Watchdog Clock Gate Control
19
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
XBAR
Peripheral Crossbar Clock Gate Control
21
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SCGC6
System Clock Gating Control Register 6
0x103C
32
read-write
n
0x0
0x0
ADC
SAR ADC Clock Gate Control
11
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
AFE
AFE Clock Gate Control
16
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
CRC
Programmable CRC Clock Gate Control
20
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
DMAMUX0
DMA MUX0 Clock Gate Control
1
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
DMAMUX1
DMA MUX1 Clock Gate Control
2
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
DMAMUX2
DMA MUX2 Clock Gate Control
3
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
DMAMUX3
DMA MUX3 Clock Gate Control
4
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
FTFA
FTFA Clock Gate Control
0
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
LPTMR
LPTMR Clock Gate Control
28
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PIT0
PIT0 Clock Gate Control
13
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
PIT1
PIT1 Clock Gate Control
14
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
RNGA
RNGA Clock Gate Control
9
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SIM_HP
SIM_HP Clock Gate Control
31
1
read-only
1
Clock is always enabled to SIM
#1
SIM_LP
SIM_LP Clock Gate Control
30
1
read-write
0
Clock is disabled
#0
1
Clock is enabled
#1
SCGC7
System Clock Gating Control Register 7
0x1040
32
read-write
n
0x0
0x0
DMA
DMA Clock Gate control.
1
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
MPU
MPU Clock Gate control.
0
1
read-write
0
Clock disabled
#0
1
Clock enabled
#1
SDID
System Device Identification Register
0x1024
32
read-only
n
0x0
0x0
ATTR
Attribute ID
16
4
read-only
0000
M0+ core
#0000
DIEID
Die ID
4
4
read-only
0000
First cut
#0000
FAMID
Metering family ID
28
4
read-only
0001
Device derivatives without LCD
#0001
0011
Device derivatives with LCD
#0011
PINID
Pincount identification
0
4
read-only
0011
44-pin
#0011
0101
64-pin
#0101
1000
100-pin
#1000
REVID
Revision ID
8
4
read-only
0001
Second Cut
#0001
SERIESID
Series ID
20
4
read-only
0011
Metering Series
#0011
SRAMSIZE
SRAM Size
12
4
read-only
0101
16kB SRAM
#0101
SUBFAMID
Sub-Family ID
24
4
read-only
0010
Device derivatives with 2 AFE enabled (AFE Channels 0 and 2 are enabled)
#0010
0011
Device derivatives with 3 AFE enabled (AFE Channels 0, 1, and 2 are enabled)
#0011
0100
Device derivatives with 4 AFE enabled
#0100
SOPT1
System Options Register 1
0x0
32
read-write
n
0x0
0x0
OSC32KSEL
32K oscillator clock select
18
2
read-write
00
OSC32KCLK
#00
01
ERCLK32K
#01
10
MCGIRCLK
#10
11
LPO
#11
SRAMSIZE
Returns the size of the system RAM
12
4
read-only
0101
16kB System RAM
#0101
SOPT1_CFG
SOPT1 Configuration Register
0x4
32
read-write
n
0x0
0x0
CMPOLPTMR0SEL
Comparator output selection for LPTMR channel0
6
1
read-write
0
CMP[1] output selected as LPTMR input[0]
#0
1
CMP[0] output selected as LPTMR input[0]
#1
LPTMR1SEL
LP timer Channel1 Select
0
2
read-write
00
Pad PTE4
#00
01
Pad PTF4
#01
10
Pad PTG1
#10
LPTMR2SEL
LP timer Channel2 Select
2
2
read-write
00
Pad PTD6
#00
01
Pad PTF3
#01
10
Pad PTG5
#10
LPTMR3SEL
LP timer Channel3 Select
4
2
read-write
00
Pad PTD5
#00
01
Pad PTG0
#01
10
Pad PTG6
#10
RAMBPEN
RAM Bitline Precharge Enable
9
1
read-write
0
Bitline precharge of system SRAM disabled during VLPR and VLPW modes.
#0
1
Bitline precharge of system SRAM enabled during VLPR and VLPW modes.
#1
RAMSBDIS
no description available
8
1
read-write
0
Source bias of System SRAM enabled during VLPR and VLPW modes.
#0
1
Source bias of System SRAM disabled during VLPR and VLPW modes.
#1
UID0
Unique Identification Register 0
0x1054
32
read-only
n
0x0
0x0
UID
Unique Identification
0
32
read-only
UID1
Unique Identification Register 1
0x1058
32
read-only
n
0x0
0x0
UID
Unique Identification
0
32
read-only
UID2
Unique Identification Register 2
0x105C
32
read-only
n
0x0
0x0
UID
Unique Identification
0
32
read-only
UID3
Unique Identification Register 3
0x1060
32
read-only
n
0x0
0x0
UID
Unique Identification
0
32
read-only
SMC
System Mode Controller
SMC
0x0
0x0
0x4
registers
n
PMCTRL
Power Mode Control register
0x1
8
read-write
n
0x0
0x0
RUNM
Run Mode Control
5
2
read-write
00
Normal Run mode (RUN)
#00
10
Very-Low-Power Run mode (VLPR)
#10
STOPA
Stop Aborted
3
1
read-only
0
The previous stop mode entry was successsful.
#0
1
The previous stop mode entry was aborted.
#1
STOPM
Stop Mode Control
0
3
read-write
000
Normal Stop (STOP)
#000
010
Very-Low-Power Stop (VLPS)
#010
100
Very-Low-Leakage Stop (VLLSx)
#100
110
Reseved
#110
PMPROT
Power Mode Protection register
0x0
8
read-write
n
0x0
0x0
AVLLS
Allow Very-Low-Leakage Stop Mode
1
1
read-write
0
Any VLLSx mode is not allowed
#0
1
Any VLLSx mode is allowed
#1
AVLP
Allow Very-Low-Power Modes
5
1
read-write
0
VLPR, VLPW, and VLPS are not allowed.
#0
1
VLPR, VLPW, and VLPS are allowed.
#1
PMSTAT
Power Mode Status register
0x3
8
read-only
n
0x0
0x0
PMSTAT
Power Mode Status
0
7
read-only
STOPCTRL
Stop Control Register
0x2
8
read-write
n
0x0
0x0
PORPO
POR Power Option
5
1
read-write
0
POR detect circuit is enabled in VLLS0
#0
1
POR detect circuit is disabled in VLLS0
#1
PSTOPO
Partial Stop Option
6
2
read-write
00
STOP - Normal Stop mode
#00
01
PSTOP1 - Partial Stop with both system and bus clocks disabled
#01
10
PSTOP2 - Partial Stop with system clock disabled and bus clock enabled
#10
VLLSM
VLLS Mode Control
0
3
read-write
000
VLLS0
#000
001
VLLS1
#001
010
VLLS2
#010
011
VLLS3
#011
SPI0
Serial Peripheral Interface
SPI
0x0
0x0
0xC
registers
n
SPI0
4
BR
SPI Baud Rate Register
0x1
8
read-write
n
0x0
0x0
SPPR
SPI Baud Rate Prescale Divisor
4
3
read-write
000
Baud rate prescaler divisor is 1.
#000
001
Baud rate prescaler divisor is 2.
#001
010
Baud rate prescaler divisor is 3.
#010
011
Baud rate prescaler divisor is 4.
#011
100
Baud rate prescaler divisor is 5.
#100
101
Baud rate prescaler divisor is 6.
#101
110
Baud rate prescaler divisor is 7.
#110
111
Baud rate prescaler divisor is 8.
#111
SPR
SPI Baud Rate Divisor
0
4
read-write
0000
Baud rate divisor is 2.
#0000
0001
Baud rate divisor is 4.
#0001
0010
Baud rate divisor is 8.
#0010
0011
Baud rate divisor is 16.
#0011
0100
Baud rate divisor is 32.
#0100
0101
Baud rate divisor is 64.
#0101
0110
Baud rate divisor is 128.
#0110
0111
Baud rate divisor is 256.
#0111
1000
Baud rate divisor is 512.
#1000
C1
SPI Control Register 1
0x3
8
read-write
n
0x0
0x0
CPHA
Clock Phase
2
1
read-write
0
First edge on SPSCK occurs at the middle of the first cycle of a data transfer.
#0
1
First edge on SPSCK occurs at the start of the first cycle of a data transfer.
#1
CPOL
Clock Polarity
3
1
read-write
0
Active-high SPI clock (idles low)
#0
1
Active-low SPI clock (idles high)
#1
LSBFE
LSB First (shifter direction)
0
1
read-write
0
SPI serial data transfers start with the most significant bit.
#0
1
SPI serial data transfers start with the least significant bit.
#1
MSTR
Master/Slave Mode Select
4
1
read-write
0
SPI module configured as a slave SPI device
#0
1
SPI module configured as a master SPI device
#1
SPE
SPI System Enable
6
1
read-write
0
SPI system inactive
#0
1
SPI system enabled
#1
SPIE
SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO (when FIFO is supported and enabled)
7
1
read-write
0
Interrupts from SPRF and MODF are inhibited-use polling (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1)
#0
1
Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are enabled (when FIFOMODE is 1)
#1
SPTIE
SPI Transmit Interrupt Enable
5
1
read-write
0
Interrupts from SPTEF inhibited (use polling)
#0
1
When SPTEF is 1, hardware interrupt requested
#1
SSOE
Slave Select Output Enable
1
1
read-write
0
When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.
#0
1
When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.
#1
C2
SPI Control Register 2
0x2
8
read-write
n
0x0
0x0
BIDIROE
Bidirectional Mode Output Enable
3
1
read-write
0
Output driver disabled so SPI data I/O pin acts as an input
#0
1
SPI I/O pin enabled as an output
#1
MODFEN
Master Mode-Fault Function Enable
4
1
read-write
0
Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
#0
1
Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
#1
RXDMAE
Receive DMA enable
2
1
read-write
0
DMA request for receive is disabled and interrupt from SPRF is allowed
#0
1
DMA request for receive is enabled and interrupt from SPRF is disabled
#1
SPC0
SPI Pin Control 0
0
1
read-write
0
SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.
#0
1
SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.
#1
SPIMODE
SPI 8-bit or 16-bit mode
6
1
read-write
0
8-bit SPI shift register, match register, and buffers
#0
1
16-bit SPI shift register, match register, and buffers
#1
SPISWAI
SPI Stop in Wait Mode
1
1
read-write
0
SPI clocks continue to operate in Wait mode.
#0
1
SPI clocks stop when the MCU enters Wait mode.
#1
SPMIE
SPI Match Interrupt Enable
7
1
read-write
0
Interrupts from SPMF inhibited (use polling)
#0
1
When SPMF is 1, requests a hardware interrupt
#1
TXDMAE
Transmit DMA enable
5
1
read-write
0
DMA request for transmit is disabled and interrupt from SPTEF is allowed
#0
1
DMA request for transmit is enabled and interrupt from SPTEF is disabled
#1
C3
SPI control register 3
0xB
8
read-write
n
0x0
0x0
FIFOMODE
FIFO mode enable
0
1
read-write
0
Buffer mode disabled
#0
1
Data available in the receive data buffer
#1
INTCLR
Interrupt clearing mechanism select
3
1
read-write
0
These interrupts are cleared when the corresponding flags are cleared depending on the state of the FIFOs
#0
1
These interrupts are cleared by writing the corresponding bits in the CI register
#1
RNFULLF_MARK
Receive FIFO nearly full watermark
4
1
read-write
0
RNFULLF is set when the receive FIFO has 48 bits or more
#0
1
RNFULLF is set when the receive FIFO has 32 bits or more
#1
RNFULLIEN
Receive FIFO nearly full interrupt enable
1
1
read-write
0
No interrupt upon RNFULLF being set
#0
1
Enable interrupts upon RNFULLF being set
#1
TNEAREF_MARK
Transmit FIFO nearly empty watermark
5
1
read-write
0
TNEAREF is set when the transmit FIFO has 16 bits or less
#0
1
TNEAREF is set when the transmit FIFO has 32 bits or less
#1
TNEARIEN
Transmit FIFO nearly empty interrupt enable
2
1
read-write
0
No interrupt upon TNEAREF being set
#0
1
Enable interrupts upon TNEAREF being set
#1
CI
SPI clear interrupt register
0xA
8
read-write
n
0x0
0x0
RNFULLFCI
Receive FIFO nearly full flag clear interrupt
2
1
write-only
RXFERR
Receive FIFO error flag
6
1
read-only
0
No receive FIFO error occurred
#0
1
A receive FIFO error occurred
#1
RXFOF
Receive FIFO overflow flag
4
1
read-only
0
Receive FIFO overflow condition has not occurred
#0
1
Receive FIFO overflow condition occurred
#1
SPRFCI
Receive FIFO full flag clear interrupt
0
1
write-only
SPTEFCI
Transmit FIFO empty flag clear interrupt
1
1
write-only
TNEAREFCI
Transmit FIFO nearly empty flag clear interrupt
3
1
write-only
TXFERR
Transmit FIFO error flag
7
1
read-only
0
No transmit FIFO error occurred
#0
1
A transmit FIFO error occurred
#1
TXFOF
Transmit FIFO overflow flag
5
1
read-only
0
Transmit FIFO overflow condition has not occurred
#0
1
Transmit FIFO overflow condition occurred
#1
DH
SPI data register high
0x7
8
read-write
n
0x0
0x0
Bits
Data (high byte)
0
8
read-write
DL
SPI Data Register low
0x6
8
read-write
n
0x0
0x0
Bits
Data (low byte)
0
8
read-write
MH
SPI match register high
0x5
8
read-write
n
0x0
0x0
Bits
Hardware compare value (high byte)
0
8
read-write
ML
SPI Match Register low
0x4
8
read-write
n
0x0
0x0
Bits
Hardware compare value (low byte)
0
8
read-write
S
SPI Status Register
0x0
8
read-only
n
0x0
0x0
MODF
Master Mode Fault Flag
4
1
read-only
0
No mode fault error
#0
1
Mode fault error detected
#1
RFIFOEF
SPI read FIFO empty flag
0
1
read-only
0
Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode will empty the read FIFO.
#0
1
Read FIFO is empty.
#1
RNFULLF
Receive FIFO nearly full flag
3
1
read-only
0
Receive FIFO has received less than 48 bits (when C3[4] is 0) or less than 32 bits (when C3[4] is 1)
#0
1
Receive FIFO has received data of an amount equal to or greater than 48 bits (when C3[4] is 0) or 32 bits (when C3[4] is 1)
#1
SPMF
SPI Match Flag
6
1
read-only
0
Value in the receive data buffer does not match the value in the MH:ML registers
#0
1
Value in the receive data buffer matches the value in the MH:ML registers
#1
SPRF
SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when FIFO is supported and enabled)
7
1
read-only
0
No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is not full (when FIFOMODE is 1)
#0
1
Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full (when FIFOMODE is 1)
#1
SPTEF
SPI Transmit Buffer Empty Flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty flag (when FIFO is supported and enabled)
5
1
read-only
0
SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when FIFOMODE is 1)
#0
1
SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when FIFOMODE is 1)
#1
TNEAREF
Transmit FIFO nearly empty flag
2
1
read-only
0
Transmit FIFO has more than 16 bits (when C3[5] is 0) or more than 32 bits (when C3[5] is 1) remaining to transmit
#0
1
Transmit FIFO has an amount of data equal to or less than 16 bits (when C3[5] is 0) or 32 bits (when C3[5] is 1) remaining to transmit
#1
TXFULLF
Transmit FIFO full flag
1
1
read-only
0
Transmit FIFO has less than 8 bytes
#0
1
Transmit FIFO has 8 bytes of data
#1
SPI1
Serial Peripheral Interface
SPI
0x0
0x0
0xC
registers
n
SPI1
5
BR
SPI Baud Rate Register
0x1
8
read-write
n
0x0
0x0
SPPR
SPI Baud Rate Prescale Divisor
4
3
read-write
000
Baud rate prescaler divisor is 1.
#000
001
Baud rate prescaler divisor is 2.
#001
010
Baud rate prescaler divisor is 3.
#010
011
Baud rate prescaler divisor is 4.
#011
100
Baud rate prescaler divisor is 5.
#100
101
Baud rate prescaler divisor is 6.
#101
110
Baud rate prescaler divisor is 7.
#110
111
Baud rate prescaler divisor is 8.
#111
SPR
SPI Baud Rate Divisor
0
4
read-write
0000
Baud rate divisor is 2.
#0000
0001
Baud rate divisor is 4.
#0001
0010
Baud rate divisor is 8.
#0010
0011
Baud rate divisor is 16.
#0011
0100
Baud rate divisor is 32.
#0100
0101
Baud rate divisor is 64.
#0101
0110
Baud rate divisor is 128.
#0110
0111
Baud rate divisor is 256.
#0111
1000
Baud rate divisor is 512.
#1000
C1
SPI Control Register 1
0x3
8
read-write
n
0x0
0x0
CPHA
Clock Phase
2
1
read-write
0
First edge on SPSCK occurs at the middle of the first cycle of a data transfer.
#0
1
First edge on SPSCK occurs at the start of the first cycle of a data transfer.
#1
CPOL
Clock Polarity
3
1
read-write
0
Active-high SPI clock (idles low)
#0
1
Active-low SPI clock (idles high)
#1
LSBFE
LSB First (shifter direction)
0
1
read-write
0
SPI serial data transfers start with the most significant bit.
#0
1
SPI serial data transfers start with the least significant bit.
#1
MSTR
Master/Slave Mode Select
4
1
read-write
0
SPI module configured as a slave SPI device
#0
1
SPI module configured as a master SPI device
#1
SPE
SPI System Enable
6
1
read-write
0
SPI system inactive
#0
1
SPI system enabled
#1
SPIE
SPI Interrupt Enable: for SPRF and MODF (when FIFO is not supported or not enabled) or for read FIFO (when FIFO is supported and enabled)
7
1
read-write
0
Interrupts from SPRF and MODF are inhibited-use polling (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are disabled (when FIFOMODE is 1)
#0
1
Request a hardware interrupt when SPRF or MODF is 1 (when FIFOMODE is not present or is 0) or Read FIFO Full Interrupts are enabled (when FIFOMODE is 1)
#1
SPTIE
SPI Transmit Interrupt Enable
5
1
read-write
0
Interrupts from SPTEF inhibited (use polling)
#0
1
When SPTEF is 1, hardware interrupt requested
#1
SSOE
Slave Select Output Enable
1
1
read-write
0
When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is SS input for mode fault. In slave mode, SS pin function is slave select input.
#0
1
When C2[MODFEN] is 0: In master mode, SS pin function is general-purpose I/O (not SPI). In slave mode, SS pin function is slave select input. When C2[MODFEN] is 1: In master mode, SS pin function is automatic SS output. In slave mode: SS pin function is slave select input.
#1
C2
SPI Control Register 2
0x2
8
read-write
n
0x0
0x0
BIDIROE
Bidirectional Mode Output Enable
3
1
read-write
0
Output driver disabled so SPI data I/O pin acts as an input
#0
1
SPI I/O pin enabled as an output
#1
MODFEN
Master Mode-Fault Function Enable
4
1
read-write
0
Mode fault function disabled, master SS pin reverts to general-purpose I/O not controlled by SPI
#0
1
Mode fault function enabled, master SS pin acts as the mode fault input or the slave select output
#1
RXDMAE
Receive DMA enable
2
1
read-write
0
DMA request for receive is disabled and interrupt from SPRF is allowed
#0
1
DMA request for receive is enabled and interrupt from SPRF is disabled
#1
SPC0
SPI Pin Control 0
0
1
read-write
0
SPI uses separate pins for data input and data output (pin mode is normal). In master mode of operation: MISO is master in and MOSI is master out. In slave mode of operation: MISO is slave out and MOSI is slave in.
#0
1
SPI configured for single-wire bidirectional operation (pin mode is bidirectional). In master mode of operation: MISO is not used by SPI; MOSI is master in when BIDIROE is 0 or master I/O when BIDIROE is 1. In slave mode of operation: MISO is slave in when BIDIROE is 0 or slave I/O when BIDIROE is 1; MOSI is not used by SPI.
#1
SPIMODE
SPI 8-bit or 16-bit mode
6
1
read-write
0
8-bit SPI shift register, match register, and buffers
#0
1
16-bit SPI shift register, match register, and buffers
#1
SPISWAI
SPI Stop in Wait Mode
1
1
read-write
0
SPI clocks continue to operate in Wait mode.
#0
1
SPI clocks stop when the MCU enters Wait mode.
#1
SPMIE
SPI Match Interrupt Enable
7
1
read-write
0
Interrupts from SPMF inhibited (use polling)
#0
1
When SPMF is 1, requests a hardware interrupt
#1
TXDMAE
Transmit DMA enable
5
1
read-write
0
DMA request for transmit is disabled and interrupt from SPTEF is allowed
#0
1
DMA request for transmit is enabled and interrupt from SPTEF is disabled
#1
C3
SPI control register 3
0xB
8
read-write
n
0x0
0x0
FIFOMODE
FIFO mode enable
0
1
read-write
0
Buffer mode disabled
#0
1
Data available in the receive data buffer
#1
INTCLR
Interrupt clearing mechanism select
3
1
read-write
0
These interrupts are cleared when the corresponding flags are cleared depending on the state of the FIFOs
#0
1
These interrupts are cleared by writing the corresponding bits in the CI register
#1
RNFULLF_MARK
Receive FIFO nearly full watermark
4
1
read-write
0
RNFULLF is set when the receive FIFO has 48 bits or more
#0
1
RNFULLF is set when the receive FIFO has 32 bits or more
#1
RNFULLIEN
Receive FIFO nearly full interrupt enable
1
1
read-write
0
No interrupt upon RNFULLF being set
#0
1
Enable interrupts upon RNFULLF being set
#1
TNEAREF_MARK
Transmit FIFO nearly empty watermark
5
1
read-write
0
TNEAREF is set when the transmit FIFO has 16 bits or less
#0
1
TNEAREF is set when the transmit FIFO has 32 bits or less
#1
TNEARIEN
Transmit FIFO nearly empty interrupt enable
2
1
read-write
0
No interrupt upon TNEAREF being set
#0
1
Enable interrupts upon TNEAREF being set
#1
CI
SPI clear interrupt register
0xA
8
read-write
n
0x0
0x0
RNFULLFCI
Receive FIFO nearly full flag clear interrupt
2
1
write-only
RXFERR
Receive FIFO error flag
6
1
read-only
0
No receive FIFO error occurred
#0
1
A receive FIFO error occurred
#1
RXFOF
Receive FIFO overflow flag
4
1
read-only
0
Receive FIFO overflow condition has not occurred
#0
1
Receive FIFO overflow condition occurred
#1
SPRFCI
Receive FIFO full flag clear interrupt
0
1
write-only
SPTEFCI
Transmit FIFO empty flag clear interrupt
1
1
write-only
TNEAREFCI
Transmit FIFO nearly empty flag clear interrupt
3
1
write-only
TXFERR
Transmit FIFO error flag
7
1
read-only
0
No transmit FIFO error occurred
#0
1
A transmit FIFO error occurred
#1
TXFOF
Transmit FIFO overflow flag
5
1
read-only
0
Transmit FIFO overflow condition has not occurred
#0
1
Transmit FIFO overflow condition occurred
#1
DH
SPI data register high
0x7
8
read-write
n
0x0
0x0
Bits
Data (high byte)
0
8
read-write
DL
SPI Data Register low
0x6
8
read-write
n
0x0
0x0
Bits
Data (low byte)
0
8
read-write
MH
SPI match register high
0x5
8
read-write
n
0x0
0x0
Bits
Hardware compare value (high byte)
0
8
read-write
ML
SPI Match Register low
0x4
8
read-write
n
0x0
0x0
Bits
Hardware compare value (low byte)
0
8
read-write
S
SPI Status Register
0x0
8
read-only
n
0x0
0x0
MODF
Master Mode Fault Flag
4
1
read-only
0
No mode fault error
#0
1
Mode fault error detected
#1
RFIFOEF
SPI read FIFO empty flag
0
1
read-only
0
Read FIFO has data. Reads of the DH:DL registers in 16-bit mode or the DL register in 8-bit mode will empty the read FIFO.
#0
1
Read FIFO is empty.
#1
RNFULLF
Receive FIFO nearly full flag
3
1
read-only
0
Receive FIFO has received less than 48 bits (when C3[4] is 0) or less than 32 bits (when C3[4] is 1)
#0
1
Receive FIFO has received data of an amount equal to or greater than 48 bits (when C3[4] is 0) or 32 bits (when C3[4] is 1)
#1
SPMF
SPI Match Flag
6
1
read-only
0
Value in the receive data buffer does not match the value in the MH:ML registers
#0
1
Value in the receive data buffer matches the value in the MH:ML registers
#1
SPRF
SPI Read Buffer Full Flag (when FIFO is not supported or not enabled) or SPI read FIFO FULL flag (when FIFO is supported and enabled)
7
1
read-only
0
No data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is not full (when FIFOMODE is 1)
#0
1
Data available in the receive data buffer (when FIFOMODE is not present or is 0) or Read FIFO is full (when FIFOMODE is 1)
#1
SPTEF
SPI Transmit Buffer Empty Flag (when FIFO is not supported or not enabled) or SPI transmit FIFO empty flag (when FIFO is supported and enabled)
5
1
read-only
0
SPI transmit buffer not empty (when FIFOMODE is not present or is 0) or SPI FIFO not empty (when FIFOMODE is 1)
#0
1
SPI transmit buffer empty (when FIFOMODE is not present or is 0) or SPI FIFO empty (when FIFOMODE is 1)
#1
TNEAREF
Transmit FIFO nearly empty flag
2
1
read-only
0
Transmit FIFO has more than 16 bits (when C3[5] is 0) or more than 32 bits (when C3[5] is 1) remaining to transmit
#0
1
Transmit FIFO has an amount of data equal to or less than 16 bits (when C3[5] is 0) or 32 bits (when C3[5] is 1) remaining to transmit
#1
TXFULLF
Transmit FIFO full flag
1
1
read-only
0
Transmit FIFO has less than 8 bytes
#0
1
Transmit FIFO has 8 bytes of data
#1
TMR0
Quad Timer
TMR
0x0
0x0
0x20
registers
n
TMR0
7
CAPT
Timer Channel Capture Register
0x4
16
read-write
n
0x0
0x0
CAPTURE
Capture Value
0
16
read-write
CMPLD1
Timer Channel Comparator Load Register 1
0x10
16
read-write
n
0x0
0x0
COMPARATOR_LOAD_1
no description available
0
16
read-write
CMPLD2
Timer Channel Comparator Load Register 2
0x12
16
read-write
n
0x0
0x0
COMPARATOR_LOAD_2
no description available
0
16
read-write
CNTR
Timer Channel Counter Register
0xA
16
read-write
n
0x0
0x0
COUNTER
no description available
0
16
read-write
COMP1
Timer Channel Compare Register 1
0x0
16
read-write
n
0x0
0x0
COMPARISON_1
Comparison Value 1
0
16
read-write
COMP2
Timer Channel Compare Register 2
0x2
16
read-write
n
0x0
0x0
COMPARISON_2
Comparison Value 2
0
16
read-write
CSCTRL
Timer Channel Comparator Status and Control Register
0x14
16
read-write
n
0x0
0x0
ALT_LOAD
Alternative Load Enable
12
1
read-write
0
Counter can be re-initialized only with the LOAD register.
#0
1
Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.
#1
CL1
Compare Load Control 1
0
2
read-write
00
Never preload
#00
01
Load upon successful compare with the value in COMP1
#01
10
Load upon successful compare with the value in COMP2
#10
CL2
Compare Load Control 2
2
2
read-write
00
Never preload
#00
01
Load upon successful compare with the value in COMP1
#01
10
Load upon successful compare with the value in COMP2
#10
DBG_EN
Debug Actions Enable
14
2
read-write
00
Continue with normal operation during debug mode. (default)
#00
01
Halt TMR counter during debug mode.
#01
10
Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).
#10
11
Both halt counter and force output to 0 during debug mode.
#11
FAULT
Fault Enable
13
1
read-write
0
Fault function disabled.
#0
1
Fault function enabled.
#1
OFLAG
Output flag
8
1
read-only
0
The OFLAG signal is low.
#0
1
The OFLAG signal is high.
#1
ROC
Reload on Capture
11
1
read-write
0
Do not reload the counter on a capture event.
#0
1
Reload the counter on a capture event.
#1
TCF1
Timer Compare 1 Interrupt Flag
4
1
read-write
TCF1EN
Timer Compare 1 Interrupt Enable
6
1
read-write
TCF2
Timer Compare 2 Interrupt Flag
5
1
read-write
TCF2EN
Timer Compare 2 Interrupt Enable
7
1
read-write
TCI
Triggered Count Initialization Control
10
1
read-write
0
Stop counter upon receiving a second trigger event while still counting from the first trigger event.
#0
1
Reload the counter upon receiving a second trigger event while still counting from the first trigger event.
#1
UP
Counting Direction Indicator
9
1
read-only
0
The last count was in the DOWN direction.
#0
1
The last count was in the UP direction.
#1
CTRL
Timer Channel Control Register
0xC
16
read-write
n
0x0
0x0
CM
Count Mode
13
3
read-write
000
No operation
#000
001
Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS].
#001
010
Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode.
#010
011
Count rising edges of primary source while secondary input high active
#011
100
Quadrature count mode, uses primary and secondary sources
#100
101
Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1.
#101
110
Edge of secondary source triggers primary count until compare
#110
111
Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.
#111
COINIT
Co-Channel Initialization
3
1
read-write
0
Co-channel counter/timers cannot force a re-initialization of this counter/timer
#0
1
Co-channel counter/timers may force a re-initialization of this counter/timer
#1
DIR
Count Direction
4
1
read-write
0
Count up.
#0
1
Count down.
#1
LENGTH
Count Length
5
1
read-write
0
Roll over.
#0
1
Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on.
#1
ONCE
Count Once
6
1
read-write
0
Count repeatedly.
#0
1
Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops.
#1
OUTMODE
Output Mode
0
3
read-write
000
Asserted while counter is active
#000
001
Clear OFLAG output on successful compare
#001
010
Set OFLAG output on successful compare
#010
011
Toggle OFLAG output on successful compare
#011
100
Toggle OFLAG output using alternating compare registers
#100
101
Set on compare, cleared on secondary source input edge
#101
110
Set on compare, cleared on counter rollover
#110
111
Enable gated clock output while counter is active
#111
PCS
Primary Count Source
9
4
read-write
0000
Counter 0 input pin
#0000
0001
Counter 1 input pin
#0001
0010
Counter 2 input pin
#0010
0011
Counter 3 input pin
#0011
0100
Counter 0 output
#0100
0101
Counter 1 output
#0101
0110
Counter 2 output
#0110
0111
Counter 3 output
#0111
1000
IP bus clock divide by 1 prescaler
#1000
1001
IP bus clock divide by 2 prescaler
#1001
1010
IP bus clock divide by 4 prescaler
#1010
1011
IP bus clock divide by 8 prescaler
#1011
1100
IP bus clock divide by 16 prescaler
#1100
1101
IP bus clock divide by 32 prescaler
#1101
1110
IP bus clock divide by 64 prescaler
#1110
1111
IP bus clock divide by 128 prescaler
#1111
SCS
Secondary Count Source
7
2
read-write
00
Counter 0 input pin
#00
01
Counter 1 input pin
#01
10
Counter 2 input pin
#10
11
Counter 3 input pin
#11
ENBL
Timer Channel Enable Register
0x1E
16
read-write
n
0x0
0x0
ENBL
Timer Channel Enable
0
4
read-write
0
Timer channel is disabled.
#0
1
Timer channel is enabled. (default)
#1
FILT
Timer Channel Input Filter Register
0x16
16
read-write
n
0x0
0x0
FILT_CNT
Input Filter Sample Count
8
3
read-write
FILT_PER
Input Filter Sample Period
0
8
read-write
HOLD
Timer Channel Hold Register
0x8
16
read-write
n
0x0
0x0
HOLD
no description available
0
16
read-write
LOAD
Timer Channel Load Register
0x6
16
read-write
n
0x0
0x0
LOAD
Timer Load Register
0
16
read-write
SCTRL
Timer Channel Status and Control Register
0xE
16
read-write
n
0x0
0x0
CAPTURE_MODE
Input Capture Mode
6
2
read-write
00
Capture function is disabled
#00
01
Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input
#01
10
Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input
#10
11
Load capture register on both edges of input
#11
EEOF
Enable External OFLAG Force
4
1
read-write
FORCE
Force OFLAG Output
2
1
write-only
IEF
Input Edge Flag
11
1
read-write
IEFIE
Input Edge Flag Interrupt Enable
10
1
read-write
INPUT
External Input Signal
8
1
read-only
IPS
Input Polarity Select
9
1
read-write
MSTR
Master Mode
5
1
read-write
OEN
Output Enable
0
1
read-write
0
The external pin is configured as an input.
#0
1
The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS.
#1
OPS
Output Polarity Select
1
1
read-write
0
True polarity.
#0
1
Inverted polarity.
#1
TCF
Timer Compare Flag
15
1
read-write
TCFIE
Timer Compare Flag Interrupt Enable
14
1
read-write
TOF
Timer Overflow Flag
13
1
read-write
TOFIE
Timer Overflow Flag Interrupt Enable
12
1
read-write
VAL
Forced OFLAG Value
3
1
read-write
TMR1
Quad Timer
TMR
0x0
0x0
0x18
registers
n
TMR1
8
CAPT
Timer Channel Capture Register
0x4
16
read-write
n
0x0
0x0
CAPTURE
Capture Value
0
16
read-write
CMPLD1
Timer Channel Comparator Load Register 1
0x10
16
read-write
n
0x0
0x0
COMPARATOR_LOAD_1
no description available
0
16
read-write
CMPLD2
Timer Channel Comparator Load Register 2
0x12
16
read-write
n
0x0
0x0
COMPARATOR_LOAD_2
no description available
0
16
read-write
CNTR
Timer Channel Counter Register
0xA
16
read-write
n
0x0
0x0
COUNTER
no description available
0
16
read-write
COMP1
Timer Channel Compare Register 1
0x0
16
read-write
n
0x0
0x0
COMPARISON_1
Comparison Value 1
0
16
read-write
COMP2
Timer Channel Compare Register 2
0x2
16
read-write
n
0x0
0x0
COMPARISON_2
Comparison Value 2
0
16
read-write
CSCTRL
Timer Channel Comparator Status and Control Register
0x14
16
read-write
n
0x0
0x0
ALT_LOAD
Alternative Load Enable
12
1
read-write
0
Counter can be re-initialized only with the LOAD register.
#0
1
Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.
#1
CL1
Compare Load Control 1
0
2
read-write
00
Never preload
#00
01
Load upon successful compare with the value in COMP1
#01
10
Load upon successful compare with the value in COMP2
#10
CL2
Compare Load Control 2
2
2
read-write
00
Never preload
#00
01
Load upon successful compare with the value in COMP1
#01
10
Load upon successful compare with the value in COMP2
#10
DBG_EN
Debug Actions Enable
14
2
read-write
00
Continue with normal operation during debug mode. (default)
#00
01
Halt TMR counter during debug mode.
#01
10
Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).
#10
11
Both halt counter and force output to 0 during debug mode.
#11
FAULT
Fault Enable
13
1
read-write
0
Fault function disabled.
#0
1
Fault function enabled.
#1
OFLAG
Output flag
8
1
read-only
0
The OFLAG signal is low.
#0
1
The OFLAG signal is high.
#1
ROC
Reload on Capture
11
1
read-write
0
Do not reload the counter on a capture event.
#0
1
Reload the counter on a capture event.
#1
TCF1
Timer Compare 1 Interrupt Flag
4
1
read-write
TCF1EN
Timer Compare 1 Interrupt Enable
6
1
read-write
TCF2
Timer Compare 2 Interrupt Flag
5
1
read-write
TCF2EN
Timer Compare 2 Interrupt Enable
7
1
read-write
TCI
Triggered Count Initialization Control
10
1
read-write
0
Stop counter upon receiving a second trigger event while still counting from the first trigger event.
#0
1
Reload the counter upon receiving a second trigger event while still counting from the first trigger event.
#1
UP
Counting Direction Indicator
9
1
read-only
0
The last count was in the DOWN direction.
#0
1
The last count was in the UP direction.
#1
CTRL
Timer Channel Control Register
0xC
16
read-write
n
0x0
0x0
CM
Count Mode
13
3
read-write
000
No operation
#000
001
Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS].
#001
010
Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode.
#010
011
Count rising edges of primary source while secondary input high active
#011
100
Quadrature count mode, uses primary and secondary sources
#100
101
Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1.
#101
110
Edge of secondary source triggers primary count until compare
#110
111
Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.
#111
COINIT
Co-Channel Initialization
3
1
read-write
0
Co-channel counter/timers cannot force a re-initialization of this counter/timer
#0
1
Co-channel counter/timers may force a re-initialization of this counter/timer
#1
DIR
Count Direction
4
1
read-write
0
Count up.
#0
1
Count down.
#1
LENGTH
Count Length
5
1
read-write
0
Roll over.
#0
1
Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on.
#1
ONCE
Count Once
6
1
read-write
0
Count repeatedly.
#0
1
Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops.
#1
OUTMODE
Output Mode
0
3
read-write
000
Asserted while counter is active
#000
001
Clear OFLAG output on successful compare
#001
010
Set OFLAG output on successful compare
#010
011
Toggle OFLAG output on successful compare
#011
100
Toggle OFLAG output using alternating compare registers
#100
101
Set on compare, cleared on secondary source input edge
#101
110
Set on compare, cleared on counter rollover
#110
111
Enable gated clock output while counter is active
#111
PCS
Primary Count Source
9
4
read-write
0000
Counter 0 input pin
#0000
0001
Counter 1 input pin
#0001
0010
Counter 2 input pin
#0010
0011
Counter 3 input pin
#0011
0100
Counter 0 output
#0100
0101
Counter 1 output
#0101
0110
Counter 2 output
#0110
0111
Counter 3 output
#0111
1000
IP bus clock divide by 1 prescaler
#1000
1001
IP bus clock divide by 2 prescaler
#1001
1010
IP bus clock divide by 4 prescaler
#1010
1011
IP bus clock divide by 8 prescaler
#1011
1100
IP bus clock divide by 16 prescaler
#1100
1101
IP bus clock divide by 32 prescaler
#1101
1110
IP bus clock divide by 64 prescaler
#1110
1111
IP bus clock divide by 128 prescaler
#1111
SCS
Secondary Count Source
7
2
read-write
00
Counter 0 input pin
#00
01
Counter 1 input pin
#01
10
Counter 2 input pin
#10
11
Counter 3 input pin
#11
FILT
Timer Channel Input Filter Register
0x16
16
read-write
n
0x0
0x0
FILT_CNT
Input Filter Sample Count
8
3
read-write
FILT_PER
Input Filter Sample Period
0
8
read-write
HOLD
Timer Channel Hold Register
0x8
16
read-write
n
0x0
0x0
HOLD
no description available
0
16
read-write
LOAD
Timer Channel Load Register
0x6
16
read-write
n
0x0
0x0
LOAD
Timer Load Register
0
16
read-write
SCTRL
Timer Channel Status and Control Register
0xE
16
read-write
n
0x0
0x0
CAPTURE_MODE
Input Capture Mode
6
2
read-write
00
Capture function is disabled
#00
01
Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input
#01
10
Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input
#10
11
Load capture register on both edges of input
#11
EEOF
Enable External OFLAG Force
4
1
read-write
FORCE
Force OFLAG Output
2
1
write-only
IEF
Input Edge Flag
11
1
read-write
IEFIE
Input Edge Flag Interrupt Enable
10
1
read-write
INPUT
External Input Signal
8
1
read-only
IPS
Input Polarity Select
9
1
read-write
MSTR
Master Mode
5
1
read-write
OEN
Output Enable
0
1
read-write
0
The external pin is configured as an input.
#0
1
The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS.
#1
OPS
Output Polarity Select
1
1
read-write
0
True polarity.
#0
1
Inverted polarity.
#1
TCF
Timer Compare Flag
15
1
read-write
TCFIE
Timer Compare Flag Interrupt Enable
14
1
read-write
TOF
Timer Overflow Flag
13
1
read-write
TOFIE
Timer Overflow Flag Interrupt Enable
12
1
read-write
VAL
Forced OFLAG Value
3
1
read-write
TMR2
Quad Timer
TMR
0x0
0x0
0x18
registers
n
TMR2
9
CAPT
Timer Channel Capture Register
0x4
16
read-write
n
0x0
0x0
CAPTURE
Capture Value
0
16
read-write
CMPLD1
Timer Channel Comparator Load Register 1
0x10
16
read-write
n
0x0
0x0
COMPARATOR_LOAD_1
no description available
0
16
read-write
CMPLD2
Timer Channel Comparator Load Register 2
0x12
16
read-write
n
0x0
0x0
COMPARATOR_LOAD_2
no description available
0
16
read-write
CNTR
Timer Channel Counter Register
0xA
16
read-write
n
0x0
0x0
COUNTER
no description available
0
16
read-write
COMP1
Timer Channel Compare Register 1
0x0
16
read-write
n
0x0
0x0
COMPARISON_1
Comparison Value 1
0
16
read-write
COMP2
Timer Channel Compare Register 2
0x2
16
read-write
n
0x0
0x0
COMPARISON_2
Comparison Value 2
0
16
read-write
CSCTRL
Timer Channel Comparator Status and Control Register
0x14
16
read-write
n
0x0
0x0
ALT_LOAD
Alternative Load Enable
12
1
read-write
0
Counter can be re-initialized only with the LOAD register.
#0
1
Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.
#1
CL1
Compare Load Control 1
0
2
read-write
00
Never preload
#00
01
Load upon successful compare with the value in COMP1
#01
10
Load upon successful compare with the value in COMP2
#10
CL2
Compare Load Control 2
2
2
read-write
00
Never preload
#00
01
Load upon successful compare with the value in COMP1
#01
10
Load upon successful compare with the value in COMP2
#10
DBG_EN
Debug Actions Enable
14
2
read-write
00
Continue with normal operation during debug mode. (default)
#00
01
Halt TMR counter during debug mode.
#01
10
Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).
#10
11
Both halt counter and force output to 0 during debug mode.
#11
FAULT
Fault Enable
13
1
read-write
0
Fault function disabled.
#0
1
Fault function enabled.
#1
OFLAG
Output flag
8
1
read-only
0
The OFLAG signal is low.
#0
1
The OFLAG signal is high.
#1
ROC
Reload on Capture
11
1
read-write
0
Do not reload the counter on a capture event.
#0
1
Reload the counter on a capture event.
#1
TCF1
Timer Compare 1 Interrupt Flag
4
1
read-write
TCF1EN
Timer Compare 1 Interrupt Enable
6
1
read-write
TCF2
Timer Compare 2 Interrupt Flag
5
1
read-write
TCF2EN
Timer Compare 2 Interrupt Enable
7
1
read-write
TCI
Triggered Count Initialization Control
10
1
read-write
0
Stop counter upon receiving a second trigger event while still counting from the first trigger event.
#0
1
Reload the counter upon receiving a second trigger event while still counting from the first trigger event.
#1
UP
Counting Direction Indicator
9
1
read-only
0
The last count was in the DOWN direction.
#0
1
The last count was in the UP direction.
#1
CTRL
Timer Channel Control Register
0xC
16
read-write
n
0x0
0x0
CM
Count Mode
13
3
read-write
000
No operation
#000
001
Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS].
#001
010
Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode.
#010
011
Count rising edges of primary source while secondary input high active
#011
100
Quadrature count mode, uses primary and secondary sources
#100
101
Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1.
#101
110
Edge of secondary source triggers primary count until compare
#110
111
Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.
#111
COINIT
Co-Channel Initialization
3
1
read-write
0
Co-channel counter/timers cannot force a re-initialization of this counter/timer
#0
1
Co-channel counter/timers may force a re-initialization of this counter/timer
#1
DIR
Count Direction
4
1
read-write
0
Count up.
#0
1
Count down.
#1
LENGTH
Count Length
5
1
read-write
0
Roll over.
#0
1
Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on.
#1
ONCE
Count Once
6
1
read-write
0
Count repeatedly.
#0
1
Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops.
#1
OUTMODE
Output Mode
0
3
read-write
000
Asserted while counter is active
#000
001
Clear OFLAG output on successful compare
#001
010
Set OFLAG output on successful compare
#010
011
Toggle OFLAG output on successful compare
#011
100
Toggle OFLAG output using alternating compare registers
#100
101
Set on compare, cleared on secondary source input edge
#101
110
Set on compare, cleared on counter rollover
#110
111
Enable gated clock output while counter is active
#111
PCS
Primary Count Source
9
4
read-write
0000
Counter 0 input pin
#0000
0001
Counter 1 input pin
#0001
0010
Counter 2 input pin
#0010
0011
Counter 3 input pin
#0011
0100
Counter 0 output
#0100
0101
Counter 1 output
#0101
0110
Counter 2 output
#0110
0111
Counter 3 output
#0111
1000
IP bus clock divide by 1 prescaler
#1000
1001
IP bus clock divide by 2 prescaler
#1001
1010
IP bus clock divide by 4 prescaler
#1010
1011
IP bus clock divide by 8 prescaler
#1011
1100
IP bus clock divide by 16 prescaler
#1100
1101
IP bus clock divide by 32 prescaler
#1101
1110
IP bus clock divide by 64 prescaler
#1110
1111
IP bus clock divide by 128 prescaler
#1111
SCS
Secondary Count Source
7
2
read-write
00
Counter 0 input pin
#00
01
Counter 1 input pin
#01
10
Counter 2 input pin
#10
11
Counter 3 input pin
#11
FILT
Timer Channel Input Filter Register
0x16
16
read-write
n
0x0
0x0
FILT_CNT
Input Filter Sample Count
8
3
read-write
FILT_PER
Input Filter Sample Period
0
8
read-write
HOLD
Timer Channel Hold Register
0x8
16
read-write
n
0x0
0x0
HOLD
no description available
0
16
read-write
LOAD
Timer Channel Load Register
0x6
16
read-write
n
0x0
0x0
LOAD
Timer Load Register
0
16
read-write
SCTRL
Timer Channel Status and Control Register
0xE
16
read-write
n
0x0
0x0
CAPTURE_MODE
Input Capture Mode
6
2
read-write
00
Capture function is disabled
#00
01
Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input
#01
10
Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input
#10
11
Load capture register on both edges of input
#11
EEOF
Enable External OFLAG Force
4
1
read-write
FORCE
Force OFLAG Output
2
1
write-only
IEF
Input Edge Flag
11
1
read-write
IEFIE
Input Edge Flag Interrupt Enable
10
1
read-write
INPUT
External Input Signal
8
1
read-only
IPS
Input Polarity Select
9
1
read-write
MSTR
Master Mode
5
1
read-write
OEN
Output Enable
0
1
read-write
0
The external pin is configured as an input.
#0
1
The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS.
#1
OPS
Output Polarity Select
1
1
read-write
0
True polarity.
#0
1
Inverted polarity.
#1
TCF
Timer Compare Flag
15
1
read-write
TCFIE
Timer Compare Flag Interrupt Enable
14
1
read-write
TOF
Timer Overflow Flag
13
1
read-write
TOFIE
Timer Overflow Flag Interrupt Enable
12
1
read-write
VAL
Forced OFLAG Value
3
1
read-write
TMR3
Quad Timer
TMR
0x0
0x0
0x18
registers
n
TMR3
10
CAPT
Timer Channel Capture Register
0x4
16
read-write
n
0x0
0x0
CAPTURE
Capture Value
0
16
read-write
CMPLD1
Timer Channel Comparator Load Register 1
0x10
16
read-write
n
0x0
0x0
COMPARATOR_LOAD_1
no description available
0
16
read-write
CMPLD2
Timer Channel Comparator Load Register 2
0x12
16
read-write
n
0x0
0x0
COMPARATOR_LOAD_2
no description available
0
16
read-write
CNTR
Timer Channel Counter Register
0xA
16
read-write
n
0x0
0x0
COUNTER
no description available
0
16
read-write
COMP1
Timer Channel Compare Register 1
0x0
16
read-write
n
0x0
0x0
COMPARISON_1
Comparison Value 1
0
16
read-write
COMP2
Timer Channel Compare Register 2
0x2
16
read-write
n
0x0
0x0
COMPARISON_2
Comparison Value 2
0
16
read-write
CSCTRL
Timer Channel Comparator Status and Control Register
0x14
16
read-write
n
0x0
0x0
ALT_LOAD
Alternative Load Enable
12
1
read-write
0
Counter can be re-initialized only with the LOAD register.
#0
1
Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.
#1
CL1
Compare Load Control 1
0
2
read-write
00
Never preload
#00
01
Load upon successful compare with the value in COMP1
#01
10
Load upon successful compare with the value in COMP2
#10
CL2
Compare Load Control 2
2
2
read-write
00
Never preload
#00
01
Load upon successful compare with the value in COMP1
#01
10
Load upon successful compare with the value in COMP2
#10
DBG_EN
Debug Actions Enable
14
2
read-write
00
Continue with normal operation during debug mode. (default)
#00
01
Halt TMR counter during debug mode.
#01
10
Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).
#10
11
Both halt counter and force output to 0 during debug mode.
#11
FAULT
Fault Enable
13
1
read-write
0
Fault function disabled.
#0
1
Fault function enabled.
#1
OFLAG
Output flag
8
1
read-only
0
The OFLAG signal is low.
#0
1
The OFLAG signal is high.
#1
ROC
Reload on Capture
11
1
read-write
0
Do not reload the counter on a capture event.
#0
1
Reload the counter on a capture event.
#1
TCF1
Timer Compare 1 Interrupt Flag
4
1
read-write
TCF1EN
Timer Compare 1 Interrupt Enable
6
1
read-write
TCF2
Timer Compare 2 Interrupt Flag
5
1
read-write
TCF2EN
Timer Compare 2 Interrupt Enable
7
1
read-write
TCI
Triggered Count Initialization Control
10
1
read-write
0
Stop counter upon receiving a second trigger event while still counting from the first trigger event.
#0
1
Reload the counter upon receiving a second trigger event while still counting from the first trigger event.
#1
UP
Counting Direction Indicator
9
1
read-only
0
The last count was in the DOWN direction.
#0
1
The last count was in the UP direction.
#1
CTRL
Timer Channel Control Register
0xC
16
read-write
n
0x0
0x0
CM
Count Mode
13
3
read-write
000
No operation
#000
001
Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising edges are counted regardless of the value of SCTRL[IPS].
#001
010
Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode.
#010
011
Count rising edges of primary source while secondary input high active
#011
100
Quadrature count mode, uses primary and secondary sources
#100
101
Count rising edges of primary source; secondary source specifies directionRising edges are counted only when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1.
#101
110
Edge of secondary source triggers primary count until compare
#110
111
Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.
#111
COINIT
Co-Channel Initialization
3
1
read-write
0
Co-channel counter/timers cannot force a re-initialization of this counter/timer
#0
1
Co-channel counter/timers may force a re-initialization of this counter/timer
#1
DIR
Count Direction
4
1
read-write
0
Count up.
#0
1
Count down.
#1
LENGTH
Count Length
5
1
read-write
0
Roll over.
#0
1
Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2 value is reached, re-initializes, counts until COMP1 value is reached, and so on.
#1
ONCE
Count Once
6
1
read-write
0
Count repeatedly.
#0
1
Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to the COMP2 value, and then stops.
#1
OUTMODE
Output Mode
0
3
read-write
000
Asserted while counter is active
#000
001
Clear OFLAG output on successful compare
#001
010
Set OFLAG output on successful compare
#010
011
Toggle OFLAG output on successful compare
#011
100
Toggle OFLAG output using alternating compare registers
#100
101
Set on compare, cleared on secondary source input edge
#101
110
Set on compare, cleared on counter rollover
#110
111
Enable gated clock output while counter is active
#111
PCS
Primary Count Source
9
4
read-write
0000
Counter 0 input pin
#0000
0001
Counter 1 input pin
#0001
0010
Counter 2 input pin
#0010
0011
Counter 3 input pin
#0011
0100
Counter 0 output
#0100
0101
Counter 1 output
#0101
0110
Counter 2 output
#0110
0111
Counter 3 output
#0111
1000
IP bus clock divide by 1 prescaler
#1000
1001
IP bus clock divide by 2 prescaler
#1001
1010
IP bus clock divide by 4 prescaler
#1010
1011
IP bus clock divide by 8 prescaler
#1011
1100
IP bus clock divide by 16 prescaler
#1100
1101
IP bus clock divide by 32 prescaler
#1101
1110
IP bus clock divide by 64 prescaler
#1110
1111
IP bus clock divide by 128 prescaler
#1111
SCS
Secondary Count Source
7
2
read-write
00
Counter 0 input pin
#00
01
Counter 1 input pin
#01
10
Counter 2 input pin
#10
11
Counter 3 input pin
#11
FILT
Timer Channel Input Filter Register
0x16
16
read-write
n
0x0
0x0
FILT_CNT
Input Filter Sample Count
8
3
read-write
FILT_PER
Input Filter Sample Period
0
8
read-write
HOLD
Timer Channel Hold Register
0x8
16
read-write
n
0x0
0x0
HOLD
no description available
0
16
read-write
LOAD
Timer Channel Load Register
0x6
16
read-write
n
0x0
0x0
LOAD
Timer Load Register
0
16
read-write
SCTRL
Timer Channel Status and Control Register
0xE
16
read-write
n
0x0
0x0
CAPTURE_MODE
Input Capture Mode
6
2
read-write
00
Capture function is disabled
#00
01
Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input
#01
10
Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input
#10
11
Load capture register on both edges of input
#11
EEOF
Enable External OFLAG Force
4
1
read-write
FORCE
Force OFLAG Output
2
1
write-only
IEF
Input Edge Flag
11
1
read-write
IEFIE
Input Edge Flag Interrupt Enable
10
1
read-write
INPUT
External Input Signal
8
1
read-only
IPS
Input Polarity Select
9
1
read-write
MSTR
Master Mode
5
1
read-write
OEN
Output Enable
0
1
read-write
0
The external pin is configured as an input.
#0
1
The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as their input see the driven value. The polarity of the signal is determined by OPS.
#1
OPS
Output Polarity Select
1
1
read-write
0
True polarity.
#0
1
Inverted polarity.
#1
TCF
Timer Compare Flag
15
1
read-write
TCFIE
Timer Compare Flag Interrupt Enable
14
1
read-write
TOF
Timer Overflow Flag
13
1
read-write
TOFIE
Timer Overflow Flag Interrupt Enable
12
1
read-write
VAL
Forced OFLAG Value
3
1
read-write
UART0
Serial Communication Interface
UART
0x0
0x0
0x17
registers
n
UART0_UART1
19
BDH
UART Baud Rate Registers: High
0x0
8
read-write
n
0x0
0x0
RXEDGIE
RxD Input Active Edge Interrupt Enable
6
1
read-write
0
Hardware interrupts from RXEDGIF disabled using polling.
#0
1
RXEDGIF interrupt request enabled.
#1
SBR
UART Baud Rate Bits
0
5
read-write
BDL
UART Baud Rate Registers: Low
0x1
8
read-write
n
0x0
0x0
SBR
UART Baud Rate Bits
0
8
read-write
C1
UART Control Register 1
0x2
8
read-write
n
0x0
0x0
ILT
Idle Line Type Select
2
1
read-write
0
Idle character bit count starts after start bit.
#0
1
Idle character bit count starts after stop bit.
#1
LOOPS
Loop Mode Select
7
1
read-write
0
Normal operation.
#0
1
Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.
#1
M
9-bit or 8-bit Mode Select
4
1
read-write
0
Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
#0
1
Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
#1
PE
Parity Enable
1
1
read-write
0
Parity function disabled.
#0
1
Parity function enabled.
#1
PT
Parity Type
0
1
read-write
0
Even parity.
#0
1
Odd parity.
#1
RSRC
Receiver Source Select
5
1
read-write
0
Selects internal loop back mode. The receiver input is internally connected to transmitter output.
#0
1
Single wire UART mode where the receiver input is connected to the transmit pin input signal.
#1
WAKE
Receiver Wakeup Method Select
3
1
read-write
0
Idle line wakeup.
#0
1
Address mark wakeup.
#1
C2
UART Control Register 2
0x3
8
read-write
n
0x0
0x0
ILIE
Idle Line Interrupt Enable
4
1
read-write
0
IDLE interrupt requests disabled.
#0
1
IDLE interrupt requests enabled.
#1
RE
Receiver Enable
2
1
read-write
0
Receiver off.
#0
1
Receiver on.
#1
RIE
Receiver Full Interrupt or DMA Transfer Enable
5
1
read-write
0
RDRF interrupt and DMA transfer requests disabled.
#0
1
RDRF interrupt or DMA transfer requests enabled.
#1
RWU
Receiver Wakeup Control
1
1
read-write
0
Normal operation.
#0
1
RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.
#1
SBK
Send Break
0
1
read-write
0
Normal transmitter operation.
#0
1
Queue break characters to be sent.
#1
TCIE
Transmission Complete Interrupt Enable
6
1
read-write
0
TC interrupt requests disabled.
#0
1
TC interrupt requests enabled.
#1
TE
Transmitter Enable
3
1
read-write
0
Transmitter off.
#0
1
Transmitter on.
#1
TIE
Transmitter Interrupt or DMA Transfer Enable.
7
1
read-write
0
TDRE interrupt and DMA transfer requests disabled.
#0
1
TDRE interrupt or DMA transfer requests enabled.
#1
C3
UART Control Register 3
0x6
8
read-write
n
0x0
0x0
FEIE
Framing Error Interrupt Enable
1
1
read-write
0
FE interrupt requests are disabled.
#0
1
FE interrupt requests are enabled.
#1
NEIE
Noise Error Interrupt Enable
2
1
read-write
0
NF interrupt requests are disabled.
#0
1
NF interrupt requests are enabled.
#1
ORIE
Overrun Error Interrupt Enable
3
1
read-write
0
OR interrupts are disabled.
#0
1
OR interrupt requests are enabled.
#1
PEIE
Parity Error Interrupt Enable
0
1
read-write
0
PF interrupt requests are disabled.
#0
1
PF interrupt requests are enabled.
#1
R8
Received Bit 8
7
1
read-only
T8
Transmit Bit 8
6
1
read-write
TXDIR
Transmitter Pin Data Direction in Single-Wire mode
5
1
read-write
0
TXD pin is an input in single wire mode.
#0
1
TXD pin is an output in single wire mode.
#1
TXINV
Transmit Data Inversion.
4
1
read-write
0
Transmit data is not inverted.
#0
1
Transmit data is inverted.
#1
C4
UART Control Register 4
0xA
8
read-write
n
0x0
0x0
BRFA
Baud Rate Fine Adjust
0
5
read-write
M10
10-bit Mode select
5
1
read-write
0
The parity bit is the ninth bit in the serial transmission.
#0
1
The parity bit is the tenth bit in the serial transmission.
#1
MAEN1
Match Address Mode Enable 1
7
1
read-write
0
All data received is transferred to the data buffer if MAEN2 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
MAEN2
Match Address Mode Enable 2
6
1
read-write
0
All data received is transferred to the data buffer if MAEN1 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
C5
UART Control Register 5
0xB
8
read-write
n
0x0
0x0
RDMAS
Receiver Full DMA Select
5
1
read-write
0
If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
#1
TDMAS
Transmitter DMA Select
7
1
read-write
0
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
#0
1
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
#1
CFIFO
UART FIFO Control Register
0x11
8
read-write
n
0x0
0x0
RXFLUSH
Receive FIFO/Buffer Flush
6
1
write-only
0
No flush operation occurs.
#0
1
All data in the receive FIFO/buffer is cleared out.
#1
RXOFE
Receive FIFO Overflow Interrupt Enable
2
1
read-write
0
RXOF flag does not generate an interrupt to the host.
#0
1
RXOF flag generates an interrupt to the host.
#1
RXUFE
Receive FIFO Underflow Interrupt Enable
0
1
read-write
0
RXUF flag does not generate an interrupt to the host.
#0
1
RXUF flag generates an interrupt to the host.
#1
TXFLUSH
Transmit FIFO/Buffer Flush
7
1
write-only
0
No flush operation occurs.
#0
1
All data in the transmit FIFO/Buffer is cleared out.
#1
TXOFE
Transmit FIFO Overflow Interrupt Enable
1
1
read-write
0
TXOF flag does not generate an interrupt to the host.
#0
1
TXOF flag generates an interrupt to the host.
#1
D
UART Data Register
0x7
8
read-write
n
0x0
0x0
RT
no description available
0
8
read-write
ED
UART Extended Data Register
0xC
8
read-only
n
0x0
0x0
NOISY
no description available
7
1
read-only
0
The dataword was received without noise.
#0
1
The data was received with noise.
#1
PARITYE
no description available
6
1
read-only
0
The dataword was received without a parity error.
#0
1
The dataword was received with a parity error.
#1
MA1
UART Match Address Registers 1
0x8
8
read-write
n
0x0
0x0
MA
Match Address
0
8
read-write
MA2
UART Match Address Registers 2
0x9
8
read-write
n
0x0
0x0
MA
Match Address
0
8
read-write
MODEM
UART Modem Register
0xD
8
read-write
n
0x0
0x0
RXRTSE
Receiver request-to-send enable
3
1
read-write
0
The receiver has no effect on RTS.
#0
1
RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].
#1
TXCTSE
Transmitter clear-to-send enable
0
1
read-write
0
CTS has no effect on the transmitter.
#0
1
Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
#1
TXRTSE
Transmitter request-to-send enable
1
1
read-write
0
The transmitter has no effect on RTS.
#0
1
When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)
#1
TXRTSPOL
Transmitter request-to-send polarity
2
1
read-write
0
Transmitter RTS is active low.
#0
1
Transmitter RTS is active high.
#1
PFIFO
UART FIFO Parameters
0x10
8
read-write
n
0x0
0x0
RXFE
Receive FIFO Enable
3
1
read-write
0
Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
#0
1
Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
#1
RXFIFOSIZE
Receive FIFO. Buffer Depth
0
3
read-only
000
Receive FIFO/Buffer depth = 1 dataword.
#000
001
Receive FIFO/Buffer depth = 4 datawords.
#001
010
Receive FIFO/Buffer depth = 8 datawords.
#010
011
Receive FIFO/Buffer depth = 16 datawords.
#011
100
Receive FIFO/Buffer depth = 32 datawords.
#100
101
Receive FIFO/Buffer depth = 64 datawords.
#101
110
Receive FIFO/Buffer depth = 128 datawords.
#110
TXFE
Transmit FIFO Enable
7
1
read-write
0
Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
#0
1
Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
#1
TXFIFOSIZE
Transmit FIFO. Buffer Depth
4
3
read-only
000
Transmit FIFO/Buffer depth = 1 dataword.
#000
001
Transmit FIFO/Buffer depth = 4 datawords.
#001
010
Transmit FIFO/Buffer depth = 8 datawords.
#010
011
Transmit FIFO/Buffer depth = 16 datawords.
#011
100
Transmit FIFO/Buffer depth = 32 datawords.
#100
101
Transmit FIFO/Buffer depth = 64 datawords.
#101
110
Transmit FIFO/Buffer depth = 128 datawords.
#110
RCFIFO
UART FIFO Receive Count
0x16
8
read-only
n
0x0
0x0
RXCOUNT
Receive Counter
0
8
read-only
RWFIFO
UART FIFO Receive Watermark
0x15
8
read-write
n
0x0
0x0
RXWATER
Receive Watermark
0
8
read-write
S1
UART Status Register 1
0x4
8
read-only
n
0x0
0x0
FE
Framing Error Flag
1
1
read-only
0
No framing error detected.
#0
1
Framing error.
#1
IDLE
Idle Line Flag
4
1
read-only
0
Receiver input is either active now or has never become active since the IDLE flag was last cleared.
#0
1
Receiver input has become idle or the flag has not been cleared since it last asserted.
#1
NF
Noise Flag
2
1
read-only
0
No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.
#0
1
At least one dataword was received with noise detected since the last time the flag was cleared.
#1
OR
Receiver Overrun Flag
3
1
read-only
0
No overrun has occurred since the last time the flag was cleared.
#0
1
Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
#1
PF
Parity Error Flag
0
1
read-only
0
No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.
#0
1
At least one dataword was received with a parity error since the last time this flag was cleared.
#1
RDRF
Receive Data Register Full Flag
5
1
read-only
0
The number of datawords in the receive buffer is less than the number indicated by RXWATER.
#0
1
The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.
#1
TC
Transmit Complete Flag
6
1
read-only
0
Transmitter active (sending data, a preamble, or a break).
#0
1
Transmitter idle (transmission activity complete).
#1
TDRE
Transmit Data Register Empty Flag
7
1
read-only
0
The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
#0
1
The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.
#1
S2
UART Status Register 2
0x5
8
read-write
n
0x0
0x0
BRK13
Break Transmit Character Length
2
1
read-write
0
Break character is 10, 11, or 12 bits long.
#0
1
Break character is 13 or 14 bits long.
#1
MSBF
Most Significant Bit First
5
1
read-write
0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
#0
1
MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].
#1
RAF
Receiver Active Flag
0
1
read-only
0
UART receiver idle/inactive waiting for a start bit.
#0
1
UART receiver active, RxD input not idle.
#1
RWUID
Receive Wakeup Idle Detect
3
1
read-write
0
S1[IDLE] is not set upon detection of an idle character.
#0
1
S1[IDLE] is set upon detection of an idle character.
#1
RXEDGIF
RxD Pin Active Edge Interrupt Flag
6
1
read-write
0
No active edge on the receive pin has occurred.
#0
1
An active edge on the receive pin has occurred.
#1
RXINV
Receive Data Inversion
4
1
read-write
0
Receive data is not inverted.
#0
1
Receive data is inverted.
#1
SFIFO
UART FIFO Status Register
0x12
8
read-write
n
0x0
0x0
RXEMPT
Receive Buffer/FIFO Empty
6
1
read-only
0
Receive buffer is not empty.
#0
1
Receive buffer is empty.
#1
RXOF
Receiver Buffer Overflow Flag
2
1
read-write
0
No receive buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer overflow has occurred since the last time the flag was cleared.
#1
RXUF
Receiver Buffer Underflow Flag
0
1
read-write
0
No receive buffer underflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer underflow has occurred since the last time the flag was cleared.
#1
TXEMPT
Transmit Buffer/FIFO Empty
7
1
read-only
0
Transmit buffer is not empty.
#0
1
Transmit buffer is empty.
#1
TXOF
Transmitter Buffer Overflow Flag
1
1
read-write
0
No transmit buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one transmit buffer overflow has occurred since the last time the flag was cleared.
#1
TCFIFO
UART FIFO Transmit Count
0x14
8
read-only
n
0x0
0x0
TXCOUNT
Transmit Counter
0
8
read-only
TWFIFO
UART FIFO Transmit Watermark
0x13
8
read-write
n
0x0
0x0
TXWATER
Transmit Watermark
0
8
read-write
UART1
Serial Communication Interface
UART
0x0
0x0
0x20
registers
n
UART0_UART1
19
BDH
UART Baud Rate Registers: High
0x0
8
read-write
n
0x0
0x0
RXEDGIE
RxD Input Active Edge Interrupt Enable
6
1
read-write
0
Hardware interrupts from RXEDGIF disabled using polling.
#0
1
RXEDGIF interrupt request enabled.
#1
SBR
UART Baud Rate Bits
0
5
read-write
BDL
UART Baud Rate Registers: Low
0x1
8
read-write
n
0x0
0x0
SBR
UART Baud Rate Bits
0
8
read-write
C1
UART Control Register 1
0x2
8
read-write
n
0x0
0x0
ILT
Idle Line Type Select
2
1
read-write
0
Idle character bit count starts after start bit.
#0
1
Idle character bit count starts after stop bit.
#1
LOOPS
Loop Mode Select
7
1
read-write
0
Normal operation.
#0
1
Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.
#1
M
9-bit or 8-bit Mode Select
4
1
read-write
0
Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
#0
1
Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
#1
PE
Parity Enable
1
1
read-write
0
Parity function disabled.
#0
1
Parity function enabled.
#1
PT
Parity Type
0
1
read-write
0
Even parity.
#0
1
Odd parity.
#1
RSRC
Receiver Source Select
5
1
read-write
0
Selects internal loop back mode. The receiver input is internally connected to transmitter output.
#0
1
Single wire UART mode where the receiver input is connected to the transmit pin input signal.
#1
WAKE
Receiver Wakeup Method Select
3
1
read-write
0
Idle line wakeup.
#0
1
Address mark wakeup.
#1
C2
UART Control Register 2
0x3
8
read-write
n
0x0
0x0
ILIE
Idle Line Interrupt Enable
4
1
read-write
0
IDLE interrupt requests disabled.
#0
1
IDLE interrupt requests enabled.
#1
RE
Receiver Enable
2
1
read-write
0
Receiver off.
#0
1
Receiver on.
#1
RIE
Receiver Full Interrupt or DMA Transfer Enable
5
1
read-write
0
RDRF interrupt and DMA transfer requests disabled.
#0
1
RDRF interrupt or DMA transfer requests enabled.
#1
RWU
Receiver Wakeup Control
1
1
read-write
0
Normal operation.
#0
1
RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.
#1
SBK
Send Break
0
1
read-write
0
Normal transmitter operation.
#0
1
Queue break characters to be sent.
#1
TCIE
Transmission Complete Interrupt Enable
6
1
read-write
0
TC interrupt requests disabled.
#0
1
TC interrupt requests enabled.
#1
TE
Transmitter Enable
3
1
read-write
0
Transmitter off.
#0
1
Transmitter on.
#1
TIE
Transmitter Interrupt or DMA Transfer Enable.
7
1
read-write
0
TDRE interrupt and DMA transfer requests disabled.
#0
1
TDRE interrupt or DMA transfer requests enabled.
#1
C3
UART Control Register 3
0x6
8
read-write
n
0x0
0x0
FEIE
Framing Error Interrupt Enable
1
1
read-write
0
FE interrupt requests are disabled.
#0
1
FE interrupt requests are enabled.
#1
NEIE
Noise Error Interrupt Enable
2
1
read-write
0
NF interrupt requests are disabled.
#0
1
NF interrupt requests are enabled.
#1
ORIE
Overrun Error Interrupt Enable
3
1
read-write
0
OR interrupts are disabled.
#0
1
OR interrupt requests are enabled.
#1
PEIE
Parity Error Interrupt Enable
0
1
read-write
0
PF interrupt requests are disabled.
#0
1
PF interrupt requests are enabled.
#1
R8
Received Bit 8
7
1
read-only
T8
Transmit Bit 8
6
1
read-write
TXDIR
Transmitter Pin Data Direction in Single-Wire mode
5
1
read-write
0
TXD pin is an input in single wire mode.
#0
1
TXD pin is an output in single wire mode.
#1
TXINV
Transmit Data Inversion.
4
1
read-write
0
Transmit data is not inverted.
#0
1
Transmit data is inverted.
#1
C4
UART Control Register 4
0xA
8
read-write
n
0x0
0x0
BRFA
Baud Rate Fine Adjust
0
5
read-write
M10
10-bit Mode select
5
1
read-write
0
The parity bit is the ninth bit in the serial transmission.
#0
1
The parity bit is the tenth bit in the serial transmission.
#1
MAEN1
Match Address Mode Enable 1
7
1
read-write
0
All data received is transferred to the data buffer if MAEN2 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
MAEN2
Match Address Mode Enable 2
6
1
read-write
0
All data received is transferred to the data buffer if MAEN1 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
C5
UART Control Register 5
0xB
8
read-write
n
0x0
0x0
RDMAS
Receiver Full DMA Select
5
1
read-write
0
If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
#1
TDMAS
Transmitter DMA Select
7
1
read-write
0
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
#0
1
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
#1
C7816
UART 7816 Control Register
0x18
8
read-write
n
0x0
0x0
ANACK
Generate NACK on Error
3
1
read-write
0
No NACK is automatically generated.
#0
1
A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected.
#1
INIT
Detect Initial Character
2
1
read-write
0
Normal operating mode. Receiver does not seek to identify initial character.
#0
1
Receiver searches for initial character.
#1
ISO_7816E
ISO-7816 Functionality Enabled
0
1
read-write
0
ISO-7816 functionality is turned off/not enabled.
#0
1
ISO-7816 functionality is turned on/enabled.
#1
ONACK
Generate NACK on Overflow
4
1
read-write
0
The received data does not generate a NACK when the receipt of the data results in an overflow event.
#0
1
If the receiver buffer overflows, a NACK is automatically sent on a received character.
#1
TTYPE
Transfer Type
1
1
read-write
0
T = 0 per the ISO-7816 specification.
#0
1
T = 1 per the ISO-7816 specification.
#1
CFIFO
UART FIFO Control Register
0x11
8
read-write
n
0x0
0x0
RXFLUSH
Receive FIFO/Buffer Flush
6
1
write-only
0
No flush operation occurs.
#0
1
All data in the receive FIFO/buffer is cleared out.
#1
RXOFE
Receive FIFO Overflow Interrupt Enable
2
1
read-write
0
RXOF flag does not generate an interrupt to the host.
#0
1
RXOF flag generates an interrupt to the host.
#1
RXUFE
Receive FIFO Underflow Interrupt Enable
0
1
read-write
0
RXUF flag does not generate an interrupt to the host.
#0
1
RXUF flag generates an interrupt to the host.
#1
TXFLUSH
Transmit FIFO/Buffer Flush
7
1
write-only
0
No flush operation occurs.
#0
1
All data in the transmit FIFO/Buffer is cleared out.
#1
TXOFE
Transmit FIFO Overflow Interrupt Enable
1
1
read-write
0
TXOF flag does not generate an interrupt to the host.
#0
1
TXOF flag generates an interrupt to the host.
#1
D
UART Data Register
0x7
8
read-write
n
0x0
0x0
RT
no description available
0
8
read-write
ED
UART Extended Data Register
0xC
8
read-only
n
0x0
0x0
NOISY
no description available
7
1
read-only
0
The dataword was received without noise.
#0
1
The data was received with noise.
#1
PARITYE
no description available
6
1
read-only
0
The dataword was received without a parity error.
#0
1
The dataword was received with a parity error.
#1
ET7816
UART 7816 Error Threshold Register
0x1E
8
read-write
n
0x0
0x0
RXTHRESHOLD
Receive NACK Threshold
0
4
read-write
TXTHRESHOLD
Transmit NACK Threshold
4
4
read-write
0
TXT asserts on the first NACK that is received.
#0
1
TXT asserts on the second NACK that is received.
#1
IE7816
UART 7816 Interrupt Enable Register
0x19
8
read-write
n
0x0
0x0
BWTE
Block Wait Timer Interrupt Enable
5
1
read-write
0
The assertion of IS7816[BWT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[BWT] results in the generation of an interrupt.
#1
CWTE
Character Wait Timer Interrupt Enable
6
1
read-write
0
The assertion of IS7816[CWT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[CWT] results in the generation of an interrupt.
#1
GTVE
Guard Timer Violated Interrupt Enable
2
1
read-write
0
The assertion of IS7816[GTV] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[GTV] results in the generation of an interrupt.
#1
INITDE
Initial Character Detected Interrupt Enable
4
1
read-write
0
The assertion of IS7816[INITD] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[INITD] results in the generation of an interrupt.
#1
RXTE
Receive Threshold Exceeded Interrupt Enable
0
1
read-write
0
The assertion of IS7816[RXT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[RXT] results in the generation of an interrupt.
#1
TXTE
Transmit Threshold Exceeded Interrupt Enable
1
1
read-write
0
The assertion of IS7816[TXT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[TXT] results in the generation of an interrupt.
#1
WTE
Wait Timer Interrupt Enable
7
1
read-write
0
The assertion of IS7816[WT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[WT] results in the generation of an interrupt.
#1
IS7816
UART 7816 Interrupt Status Register
0x1A
8
read-write
n
0x0
0x0
BWT
Block Wait Timer Interrupt
5
1
read-write
0
Block wait time (BWT) has not been violated.
#0
1
Block wait time (BWT) has been violated.
#1
CWT
Character Wait Timer Interrupt
6
1
read-write
0
Character wait time (CWT) has not been violated.
#0
1
Character wait time (CWT) has been violated.
#1
GTV
Guard Timer Violated Interrupt
2
1
read-write
0
A guard time (GT, CGT, or BGT) has not been violated.
#0
1
A guard time (GT, CGT, or BGT) has been violated.
#1
INITD
Initial Character Detected Interrupt
4
1
read-write
0
A valid initial character has not been received.
#0
1
A valid initial character has been received.
#1
RXT
Receive Threshold Exceeded Interrupt
0
1
read-write
0
The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD].
#0
1
The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
#1
TXT
Transmit Threshold Exceeded Interrupt
1
1
read-write
0
The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD].
#0
1
The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD].
#1
WT
Wait Timer Interrupt
7
1
read-write
0
Wait time (WT) has not been violated.
#0
1
Wait time (WT) has been violated.
#1
MA1
UART Match Address Registers 1
0x8
8
read-write
n
0x0
0x0
MA
Match Address
0
8
read-write
MA2
UART Match Address Registers 2
0x9
8
read-write
n
0x0
0x0
MA
Match Address
0
8
read-write
MODEM
UART Modem Register
0xD
8
read-write
n
0x0
0x0
RXRTSE
Receiver request-to-send enable
3
1
read-write
0
The receiver has no effect on RTS.
#0
1
RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].
#1
TXCTSE
Transmitter clear-to-send enable
0
1
read-write
0
CTS has no effect on the transmitter.
#0
1
Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
#1
TXRTSE
Transmitter request-to-send enable
1
1
read-write
0
The transmitter has no effect on RTS.
#0
1
When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)
#1
TXRTSPOL
Transmitter request-to-send polarity
2
1
read-write
0
Transmitter RTS is active low.
#0
1
Transmitter RTS is active high.
#1
PFIFO
UART FIFO Parameters
0x10
8
read-write
n
0x0
0x0
RXFE
Receive FIFO Enable
3
1
read-write
0
Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
#0
1
Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
#1
RXFIFOSIZE
Receive FIFO. Buffer Depth
0
3
read-only
000
Receive FIFO/Buffer depth = 1 dataword.
#000
001
Receive FIFO/Buffer depth = 4 datawords.
#001
010
Receive FIFO/Buffer depth = 8 datawords.
#010
011
Receive FIFO/Buffer depth = 16 datawords.
#011
100
Receive FIFO/Buffer depth = 32 datawords.
#100
101
Receive FIFO/Buffer depth = 64 datawords.
#101
110
Receive FIFO/Buffer depth = 128 datawords.
#110
TXFE
Transmit FIFO Enable
7
1
read-write
0
Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
#0
1
Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
#1
TXFIFOSIZE
Transmit FIFO. Buffer Depth
4
3
read-only
000
Transmit FIFO/Buffer depth = 1 dataword.
#000
001
Transmit FIFO/Buffer depth = 4 datawords.
#001
010
Transmit FIFO/Buffer depth = 8 datawords.
#010
011
Transmit FIFO/Buffer depth = 16 datawords.
#011
100
Transmit FIFO/Buffer depth = 32 datawords.
#100
101
Transmit FIFO/Buffer depth = 64 datawords.
#101
110
Transmit FIFO/Buffer depth = 128 datawords.
#110
RCFIFO
UART FIFO Receive Count
0x16
8
read-only
n
0x0
0x0
RXCOUNT
Receive Counter
0
8
read-only
RWFIFO
UART FIFO Receive Watermark
0x15
8
read-write
n
0x0
0x0
RXWATER
Receive Watermark
0
8
read-write
S1
UART Status Register 1
0x4
8
read-only
n
0x0
0x0
FE
Framing Error Flag
1
1
read-only
0
No framing error detected.
#0
1
Framing error.
#1
IDLE
Idle Line Flag
4
1
read-only
0
Receiver input is either active now or has never become active since the IDLE flag was last cleared.
#0
1
Receiver input has become idle or the flag has not been cleared since it last asserted.
#1
NF
Noise Flag
2
1
read-only
0
No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.
#0
1
At least one dataword was received with noise detected since the last time the flag was cleared.
#1
OR
Receiver Overrun Flag
3
1
read-only
0
No overrun has occurred since the last time the flag was cleared.
#0
1
Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
#1
PF
Parity Error Flag
0
1
read-only
0
No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.
#0
1
At least one dataword was received with a parity error since the last time this flag was cleared.
#1
RDRF
Receive Data Register Full Flag
5
1
read-only
0
The number of datawords in the receive buffer is less than the number indicated by RXWATER.
#0
1
The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.
#1
TC
Transmit Complete Flag
6
1
read-only
0
Transmitter active (sending data, a preamble, or a break).
#0
1
Transmitter idle (transmission activity complete).
#1
TDRE
Transmit Data Register Empty Flag
7
1
read-only
0
The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
#0
1
The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.
#1
S2
UART Status Register 2
0x5
8
read-write
n
0x0
0x0
BRK13
Break Transmit Character Length
2
1
read-write
0
Break character is 10, 11, or 12 bits long.
#0
1
Break character is 13 or 14 bits long.
#1
MSBF
Most Significant Bit First
5
1
read-write
0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
#0
1
MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].
#1
RAF
Receiver Active Flag
0
1
read-only
0
UART receiver idle/inactive waiting for a start bit.
#0
1
UART receiver active, RxD input not idle.
#1
RWUID
Receive Wakeup Idle Detect
3
1
read-write
0
S1[IDLE] is not set upon detection of an idle character.
#0
1
S1[IDLE] is set upon detection of an idle character.
#1
RXEDGIF
RxD Pin Active Edge Interrupt Flag
6
1
read-write
0
No active edge on the receive pin has occurred.
#0
1
An active edge on the receive pin has occurred.
#1
RXINV
Receive Data Inversion
4
1
read-write
0
Receive data is not inverted.
#0
1
Receive data is inverted.
#1
SFIFO
UART FIFO Status Register
0x12
8
read-write
n
0x0
0x0
RXEMPT
Receive Buffer/FIFO Empty
6
1
read-only
0
Receive buffer is not empty.
#0
1
Receive buffer is empty.
#1
RXOF
Receiver Buffer Overflow Flag
2
1
read-write
0
No receive buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer overflow has occurred since the last time the flag was cleared.
#1
RXUF
Receiver Buffer Underflow Flag
0
1
read-write
0
No receive buffer underflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer underflow has occurred since the last time the flag was cleared.
#1
TXEMPT
Transmit Buffer/FIFO Empty
7
1
read-only
0
Transmit buffer is not empty.
#0
1
Transmit buffer is empty.
#1
TXOF
Transmitter Buffer Overflow Flag
1
1
read-write
0
No transmit buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one transmit buffer overflow has occurred since the last time the flag was cleared.
#1
TCFIFO
UART FIFO Transmit Count
0x14
8
read-only
n
0x0
0x0
TXCOUNT
Transmit Counter
0
8
read-only
TL7816
UART 7816 Transmit Length Register
0x1F
8
read-write
n
0x0
0x0
TLEN
Transmit Length
0
8
read-write
TWFIFO
UART FIFO Transmit Watermark
0x13
8
read-write
n
0x0
0x0
TXWATER
Transmit Watermark
0
8
read-write
WF7816
UART 7816 Wait FD Register
0x1D
8
read-write
n
0x0
0x0
GTFD
FD Multiplier
0
8
read-write
WN7816
UART 7816 Wait N Register
0x1C
8
read-write
n
0x0
0x0
GTN
Guard Band N
0
8
read-write
WP7816T0
UART 7816 Wait Parameter Register
UART1
0x1B
8
read-write
n
0x0
0x0
WI
Wait Time Integer (C7816[TTYPE] = 0)
0
8
read-write
WP7816T1
UART 7816 Wait Parameter Register
UART1
0x1B
8
read-write
n
0x0
0x0
BWI
Block Wait Time Integer(C7816[TTYPE] = 1)
0
4
read-write
CWI
Character Wait Time Integer (C7816[TTYPE] = 1)
4
4
read-write
UART2
Serial Communication Interface
UART
0x0
0x0
0x17
registers
n
UART2_UART3
20
BDH
UART Baud Rate Registers: High
0x0
8
read-write
n
0x0
0x0
RXEDGIE
RxD Input Active Edge Interrupt Enable
6
1
read-write
0
Hardware interrupts from RXEDGIF disabled using polling.
#0
1
RXEDGIF interrupt request enabled.
#1
SBR
UART Baud Rate Bits
0
5
read-write
BDL
UART Baud Rate Registers: Low
0x1
8
read-write
n
0x0
0x0
SBR
UART Baud Rate Bits
0
8
read-write
C1
UART Control Register 1
0x2
8
read-write
n
0x0
0x0
ILT
Idle Line Type Select
2
1
read-write
0
Idle character bit count starts after start bit.
#0
1
Idle character bit count starts after stop bit.
#1
LOOPS
Loop Mode Select
7
1
read-write
0
Normal operation.
#0
1
Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.
#1
M
9-bit or 8-bit Mode Select
4
1
read-write
0
Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
#0
1
Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
#1
PE
Parity Enable
1
1
read-write
0
Parity function disabled.
#0
1
Parity function enabled.
#1
PT
Parity Type
0
1
read-write
0
Even parity.
#0
1
Odd parity.
#1
RSRC
Receiver Source Select
5
1
read-write
0
Selects internal loop back mode. The receiver input is internally connected to transmitter output.
#0
1
Single wire UART mode where the receiver input is connected to the transmit pin input signal.
#1
WAKE
Receiver Wakeup Method Select
3
1
read-write
0
Idle line wakeup.
#0
1
Address mark wakeup.
#1
C2
UART Control Register 2
0x3
8
read-write
n
0x0
0x0
ILIE
Idle Line Interrupt Enable
4
1
read-write
0
IDLE interrupt requests disabled.
#0
1
IDLE interrupt requests enabled.
#1
RE
Receiver Enable
2
1
read-write
0
Receiver off.
#0
1
Receiver on.
#1
RIE
Receiver Full Interrupt or DMA Transfer Enable
5
1
read-write
0
RDRF interrupt and DMA transfer requests disabled.
#0
1
RDRF interrupt or DMA transfer requests enabled.
#1
RWU
Receiver Wakeup Control
1
1
read-write
0
Normal operation.
#0
1
RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.
#1
SBK
Send Break
0
1
read-write
0
Normal transmitter operation.
#0
1
Queue break characters to be sent.
#1
TCIE
Transmission Complete Interrupt Enable
6
1
read-write
0
TC interrupt requests disabled.
#0
1
TC interrupt requests enabled.
#1
TE
Transmitter Enable
3
1
read-write
0
Transmitter off.
#0
1
Transmitter on.
#1
TIE
Transmitter Interrupt or DMA Transfer Enable.
7
1
read-write
0
TDRE interrupt and DMA transfer requests disabled.
#0
1
TDRE interrupt or DMA transfer requests enabled.
#1
C3
UART Control Register 3
0x6
8
read-write
n
0x0
0x0
FEIE
Framing Error Interrupt Enable
1
1
read-write
0
FE interrupt requests are disabled.
#0
1
FE interrupt requests are enabled.
#1
NEIE
Noise Error Interrupt Enable
2
1
read-write
0
NF interrupt requests are disabled.
#0
1
NF interrupt requests are enabled.
#1
ORIE
Overrun Error Interrupt Enable
3
1
read-write
0
OR interrupts are disabled.
#0
1
OR interrupt requests are enabled.
#1
PEIE
Parity Error Interrupt Enable
0
1
read-write
0
PF interrupt requests are disabled.
#0
1
PF interrupt requests are enabled.
#1
R8
Received Bit 8
7
1
read-only
T8
Transmit Bit 8
6
1
read-write
TXDIR
Transmitter Pin Data Direction in Single-Wire mode
5
1
read-write
0
TXD pin is an input in single wire mode.
#0
1
TXD pin is an output in single wire mode.
#1
TXINV
Transmit Data Inversion.
4
1
read-write
0
Transmit data is not inverted.
#0
1
Transmit data is inverted.
#1
C4
UART Control Register 4
0xA
8
read-write
n
0x0
0x0
BRFA
Baud Rate Fine Adjust
0
5
read-write
M10
10-bit Mode select
5
1
read-write
0
The parity bit is the ninth bit in the serial transmission.
#0
1
The parity bit is the tenth bit in the serial transmission.
#1
MAEN1
Match Address Mode Enable 1
7
1
read-write
0
All data received is transferred to the data buffer if MAEN2 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
MAEN2
Match Address Mode Enable 2
6
1
read-write
0
All data received is transferred to the data buffer if MAEN1 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
C5
UART Control Register 5
0xB
8
read-write
n
0x0
0x0
RDMAS
Receiver Full DMA Select
5
1
read-write
0
If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
#1
TDMAS
Transmitter DMA Select
7
1
read-write
0
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
#0
1
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
#1
CFIFO
UART FIFO Control Register
0x11
8
read-write
n
0x0
0x0
RXFLUSH
Receive FIFO/Buffer Flush
6
1
write-only
0
No flush operation occurs.
#0
1
All data in the receive FIFO/buffer is cleared out.
#1
RXOFE
Receive FIFO Overflow Interrupt Enable
2
1
read-write
0
RXOF flag does not generate an interrupt to the host.
#0
1
RXOF flag generates an interrupt to the host.
#1
RXUFE
Receive FIFO Underflow Interrupt Enable
0
1
read-write
0
RXUF flag does not generate an interrupt to the host.
#0
1
RXUF flag generates an interrupt to the host.
#1
TXFLUSH
Transmit FIFO/Buffer Flush
7
1
write-only
0
No flush operation occurs.
#0
1
All data in the transmit FIFO/Buffer is cleared out.
#1
TXOFE
Transmit FIFO Overflow Interrupt Enable
1
1
read-write
0
TXOF flag does not generate an interrupt to the host.
#0
1
TXOF flag generates an interrupt to the host.
#1
D
UART Data Register
0x7
8
read-write
n
0x0
0x0
RT
no description available
0
8
read-write
ED
UART Extended Data Register
0xC
8
read-only
n
0x0
0x0
NOISY
no description available
7
1
read-only
0
The dataword was received without noise.
#0
1
The data was received with noise.
#1
PARITYE
no description available
6
1
read-only
0
The dataword was received without a parity error.
#0
1
The dataword was received with a parity error.
#1
MA1
UART Match Address Registers 1
0x8
8
read-write
n
0x0
0x0
MA
Match Address
0
8
read-write
MA2
UART Match Address Registers 2
0x9
8
read-write
n
0x0
0x0
MA
Match Address
0
8
read-write
MODEM
UART Modem Register
0xD
8
read-write
n
0x0
0x0
RXRTSE
Receiver request-to-send enable
3
1
read-write
0
The receiver has no effect on RTS.
#0
1
RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].
#1
TXCTSE
Transmitter clear-to-send enable
0
1
read-write
0
CTS has no effect on the transmitter.
#0
1
Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
#1
TXRTSE
Transmitter request-to-send enable
1
1
read-write
0
The transmitter has no effect on RTS.
#0
1
When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)
#1
TXRTSPOL
Transmitter request-to-send polarity
2
1
read-write
0
Transmitter RTS is active low.
#0
1
Transmitter RTS is active high.
#1
PFIFO
UART FIFO Parameters
0x10
8
read-write
n
0x0
0x0
RXFE
Receive FIFO Enable
3
1
read-write
0
Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
#0
1
Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
#1
RXFIFOSIZE
Receive FIFO. Buffer Depth
0
3
read-only
000
Receive FIFO/Buffer depth = 1 dataword.
#000
001
Receive FIFO/Buffer depth = 4 datawords.
#001
010
Receive FIFO/Buffer depth = 8 datawords.
#010
011
Receive FIFO/Buffer depth = 16 datawords.
#011
100
Receive FIFO/Buffer depth = 32 datawords.
#100
101
Receive FIFO/Buffer depth = 64 datawords.
#101
110
Receive FIFO/Buffer depth = 128 datawords.
#110
TXFE
Transmit FIFO Enable
7
1
read-write
0
Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
#0
1
Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
#1
TXFIFOSIZE
Transmit FIFO. Buffer Depth
4
3
read-only
000
Transmit FIFO/Buffer depth = 1 dataword.
#000
001
Transmit FIFO/Buffer depth = 4 datawords.
#001
010
Transmit FIFO/Buffer depth = 8 datawords.
#010
011
Transmit FIFO/Buffer depth = 16 datawords.
#011
100
Transmit FIFO/Buffer depth = 32 datawords.
#100
101
Transmit FIFO/Buffer depth = 64 datawords.
#101
110
Transmit FIFO/Buffer depth = 128 datawords.
#110
RCFIFO
UART FIFO Receive Count
0x16
8
read-only
n
0x0
0x0
RXCOUNT
Receive Counter
0
8
read-only
RWFIFO
UART FIFO Receive Watermark
0x15
8
read-write
n
0x0
0x0
RXWATER
Receive Watermark
0
8
read-write
S1
UART Status Register 1
0x4
8
read-only
n
0x0
0x0
FE
Framing Error Flag
1
1
read-only
0
No framing error detected.
#0
1
Framing error.
#1
IDLE
Idle Line Flag
4
1
read-only
0
Receiver input is either active now or has never become active since the IDLE flag was last cleared.
#0
1
Receiver input has become idle or the flag has not been cleared since it last asserted.
#1
NF
Noise Flag
2
1
read-only
0
No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.
#0
1
At least one dataword was received with noise detected since the last time the flag was cleared.
#1
OR
Receiver Overrun Flag
3
1
read-only
0
No overrun has occurred since the last time the flag was cleared.
#0
1
Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
#1
PF
Parity Error Flag
0
1
read-only
0
No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.
#0
1
At least one dataword was received with a parity error since the last time this flag was cleared.
#1
RDRF
Receive Data Register Full Flag
5
1
read-only
0
The number of datawords in the receive buffer is less than the number indicated by RXWATER.
#0
1
The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.
#1
TC
Transmit Complete Flag
6
1
read-only
0
Transmitter active (sending data, a preamble, or a break).
#0
1
Transmitter idle (transmission activity complete).
#1
TDRE
Transmit Data Register Empty Flag
7
1
read-only
0
The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
#0
1
The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.
#1
S2
UART Status Register 2
0x5
8
read-write
n
0x0
0x0
BRK13
Break Transmit Character Length
2
1
read-write
0
Break character is 10, 11, or 12 bits long.
#0
1
Break character is 13 or 14 bits long.
#1
MSBF
Most Significant Bit First
5
1
read-write
0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
#0
1
MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].
#1
RAF
Receiver Active Flag
0
1
read-only
0
UART receiver idle/inactive waiting for a start bit.
#0
1
UART receiver active, RxD input not idle.
#1
RWUID
Receive Wakeup Idle Detect
3
1
read-write
0
S1[IDLE] is not set upon detection of an idle character.
#0
1
S1[IDLE] is set upon detection of an idle character.
#1
RXEDGIF
RxD Pin Active Edge Interrupt Flag
6
1
read-write
0
No active edge on the receive pin has occurred.
#0
1
An active edge on the receive pin has occurred.
#1
RXINV
Receive Data Inversion
4
1
read-write
0
Receive data is not inverted.
#0
1
Receive data is inverted.
#1
SFIFO
UART FIFO Status Register
0x12
8
read-write
n
0x0
0x0
RXEMPT
Receive Buffer/FIFO Empty
6
1
read-only
0
Receive buffer is not empty.
#0
1
Receive buffer is empty.
#1
RXOF
Receiver Buffer Overflow Flag
2
1
read-write
0
No receive buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer overflow has occurred since the last time the flag was cleared.
#1
RXUF
Receiver Buffer Underflow Flag
0
1
read-write
0
No receive buffer underflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer underflow has occurred since the last time the flag was cleared.
#1
TXEMPT
Transmit Buffer/FIFO Empty
7
1
read-only
0
Transmit buffer is not empty.
#0
1
Transmit buffer is empty.
#1
TXOF
Transmitter Buffer Overflow Flag
1
1
read-write
0
No transmit buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one transmit buffer overflow has occurred since the last time the flag was cleared.
#1
TCFIFO
UART FIFO Transmit Count
0x14
8
read-only
n
0x0
0x0
TXCOUNT
Transmit Counter
0
8
read-only
TWFIFO
UART FIFO Transmit Watermark
0x13
8
read-write
n
0x0
0x0
TXWATER
Transmit Watermark
0
8
read-write
UART3
Serial Communication Interface
UART
0x0
0x0
0x20
registers
n
UART2_UART3
20
BDH
UART Baud Rate Registers: High
0x0
8
read-write
n
0x0
0x0
RXEDGIE
RxD Input Active Edge Interrupt Enable
6
1
read-write
0
Hardware interrupts from RXEDGIF disabled using polling.
#0
1
RXEDGIF interrupt request enabled.
#1
SBR
UART Baud Rate Bits
0
5
read-write
BDL
UART Baud Rate Registers: Low
0x1
8
read-write
n
0x0
0x0
SBR
UART Baud Rate Bits
0
8
read-write
C1
UART Control Register 1
0x2
8
read-write
n
0x0
0x0
ILT
Idle Line Type Select
2
1
read-write
0
Idle character bit count starts after start bit.
#0
1
Idle character bit count starts after stop bit.
#1
LOOPS
Loop Mode Select
7
1
read-write
0
Normal operation.
#0
1
Loop mode where transmitter output is internally connected to receiver input. The receiver input is determined by RSRC.
#1
M
9-bit or 8-bit Mode Select
4
1
read-write
0
Normal-start + 8 data bits (MSB/LSB first as determined by MSBF) + stop.
#0
1
Use-start + 9 data bits (MSB/LSB first as determined by MSBF) + stop.
#1
PE
Parity Enable
1
1
read-write
0
Parity function disabled.
#0
1
Parity function enabled.
#1
PT
Parity Type
0
1
read-write
0
Even parity.
#0
1
Odd parity.
#1
RSRC
Receiver Source Select
5
1
read-write
0
Selects internal loop back mode. The receiver input is internally connected to transmitter output.
#0
1
Single wire UART mode where the receiver input is connected to the transmit pin input signal.
#1
WAKE
Receiver Wakeup Method Select
3
1
read-write
0
Idle line wakeup.
#0
1
Address mark wakeup.
#1
C2
UART Control Register 2
0x3
8
read-write
n
0x0
0x0
ILIE
Idle Line Interrupt Enable
4
1
read-write
0
IDLE interrupt requests disabled.
#0
1
IDLE interrupt requests enabled.
#1
RE
Receiver Enable
2
1
read-write
0
Receiver off.
#0
1
Receiver on.
#1
RIE
Receiver Full Interrupt or DMA Transfer Enable
5
1
read-write
0
RDRF interrupt and DMA transfer requests disabled.
#0
1
RDRF interrupt or DMA transfer requests enabled.
#1
RWU
Receiver Wakeup Control
1
1
read-write
0
Normal operation.
#0
1
RWU enables the wakeup function and inhibits further receiver interrupt requests. Normally, hardware wakes the receiver by automatically clearing RWU.
#1
SBK
Send Break
0
1
read-write
0
Normal transmitter operation.
#0
1
Queue break characters to be sent.
#1
TCIE
Transmission Complete Interrupt Enable
6
1
read-write
0
TC interrupt requests disabled.
#0
1
TC interrupt requests enabled.
#1
TE
Transmitter Enable
3
1
read-write
0
Transmitter off.
#0
1
Transmitter on.
#1
TIE
Transmitter Interrupt or DMA Transfer Enable.
7
1
read-write
0
TDRE interrupt and DMA transfer requests disabled.
#0
1
TDRE interrupt or DMA transfer requests enabled.
#1
C3
UART Control Register 3
0x6
8
read-write
n
0x0
0x0
FEIE
Framing Error Interrupt Enable
1
1
read-write
0
FE interrupt requests are disabled.
#0
1
FE interrupt requests are enabled.
#1
NEIE
Noise Error Interrupt Enable
2
1
read-write
0
NF interrupt requests are disabled.
#0
1
NF interrupt requests are enabled.
#1
ORIE
Overrun Error Interrupt Enable
3
1
read-write
0
OR interrupts are disabled.
#0
1
OR interrupt requests are enabled.
#1
PEIE
Parity Error Interrupt Enable
0
1
read-write
0
PF interrupt requests are disabled.
#0
1
PF interrupt requests are enabled.
#1
R8
Received Bit 8
7
1
read-only
T8
Transmit Bit 8
6
1
read-write
TXDIR
Transmitter Pin Data Direction in Single-Wire mode
5
1
read-write
0
TXD pin is an input in single wire mode.
#0
1
TXD pin is an output in single wire mode.
#1
TXINV
Transmit Data Inversion.
4
1
read-write
0
Transmit data is not inverted.
#0
1
Transmit data is inverted.
#1
C4
UART Control Register 4
0xA
8
read-write
n
0x0
0x0
BRFA
Baud Rate Fine Adjust
0
5
read-write
M10
10-bit Mode select
5
1
read-write
0
The parity bit is the ninth bit in the serial transmission.
#0
1
The parity bit is the tenth bit in the serial transmission.
#1
MAEN1
Match Address Mode Enable 1
7
1
read-write
0
All data received is transferred to the data buffer if MAEN2 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA1 register. If no match occurs, the data is discarded. If match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
MAEN2
Match Address Mode Enable 2
6
1
read-write
0
All data received is transferred to the data buffer if MAEN1 is cleared.
#0
1
All data received with the most significant bit cleared, is discarded. All data received with the most significant bit set, is compared with contents of MA2 register. If no match occurs, the data is discarded. If a match occurs, data is transferred to the data buffer. This field must be cleared when C7816[ISO7816E] is set/enabled.
#1
C5
UART Control Register 5
0xB
8
read-write
n
0x0
0x0
RDMAS
Receiver Full DMA Select
5
1
read-write
0
If C2[RIE] and S1[RDRF] are set, the RDFR interrupt request signal is asserted to request an interrupt service.
#0
1
If C2[RIE] and S1[RDRF] are set, the RDRF DMA request signal is asserted to request a DMA transfer.
#1
TDMAS
Transmitter DMA Select
7
1
read-write
0
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE interrupt request signal is asserted to request interrupt service.
#0
1
If C2[TIE] is set and the S1[TDRE] flag is set, the TDRE DMA request signal is asserted to request a DMA transfer.
#1
C7816
UART 7816 Control Register
0x18
8
read-write
n
0x0
0x0
ANACK
Generate NACK on Error
3
1
read-write
0
No NACK is automatically generated.
#0
1
A NACK is automatically generated if a parity error is detected or if an invalid initial character is detected.
#1
INIT
Detect Initial Character
2
1
read-write
0
Normal operating mode. Receiver does not seek to identify initial character.
#0
1
Receiver searches for initial character.
#1
ISO_7816E
ISO-7816 Functionality Enabled
0
1
read-write
0
ISO-7816 functionality is turned off/not enabled.
#0
1
ISO-7816 functionality is turned on/enabled.
#1
ONACK
Generate NACK on Overflow
4
1
read-write
0
The received data does not generate a NACK when the receipt of the data results in an overflow event.
#0
1
If the receiver buffer overflows, a NACK is automatically sent on a received character.
#1
TTYPE
Transfer Type
1
1
read-write
0
T = 0 per the ISO-7816 specification.
#0
1
T = 1 per the ISO-7816 specification.
#1
CFIFO
UART FIFO Control Register
0x11
8
read-write
n
0x0
0x0
RXFLUSH
Receive FIFO/Buffer Flush
6
1
write-only
0
No flush operation occurs.
#0
1
All data in the receive FIFO/buffer is cleared out.
#1
RXOFE
Receive FIFO Overflow Interrupt Enable
2
1
read-write
0
RXOF flag does not generate an interrupt to the host.
#0
1
RXOF flag generates an interrupt to the host.
#1
RXUFE
Receive FIFO Underflow Interrupt Enable
0
1
read-write
0
RXUF flag does not generate an interrupt to the host.
#0
1
RXUF flag generates an interrupt to the host.
#1
TXFLUSH
Transmit FIFO/Buffer Flush
7
1
write-only
0
No flush operation occurs.
#0
1
All data in the transmit FIFO/Buffer is cleared out.
#1
TXOFE
Transmit FIFO Overflow Interrupt Enable
1
1
read-write
0
TXOF flag does not generate an interrupt to the host.
#0
1
TXOF flag generates an interrupt to the host.
#1
D
UART Data Register
0x7
8
read-write
n
0x0
0x0
RT
no description available
0
8
read-write
ED
UART Extended Data Register
0xC
8
read-only
n
0x0
0x0
NOISY
no description available
7
1
read-only
0
The dataword was received without noise.
#0
1
The data was received with noise.
#1
PARITYE
no description available
6
1
read-only
0
The dataword was received without a parity error.
#0
1
The dataword was received with a parity error.
#1
ET7816
UART 7816 Error Threshold Register
0x1E
8
read-write
n
0x0
0x0
RXTHRESHOLD
Receive NACK Threshold
0
4
read-write
TXTHRESHOLD
Transmit NACK Threshold
4
4
read-write
0
TXT asserts on the first NACK that is received.
#0
1
TXT asserts on the second NACK that is received.
#1
IE7816
UART 7816 Interrupt Enable Register
0x19
8
read-write
n
0x0
0x0
BWTE
Block Wait Timer Interrupt Enable
5
1
read-write
0
The assertion of IS7816[BWT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[BWT] results in the generation of an interrupt.
#1
CWTE
Character Wait Timer Interrupt Enable
6
1
read-write
0
The assertion of IS7816[CWT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[CWT] results in the generation of an interrupt.
#1
GTVE
Guard Timer Violated Interrupt Enable
2
1
read-write
0
The assertion of IS7816[GTV] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[GTV] results in the generation of an interrupt.
#1
INITDE
Initial Character Detected Interrupt Enable
4
1
read-write
0
The assertion of IS7816[INITD] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[INITD] results in the generation of an interrupt.
#1
RXTE
Receive Threshold Exceeded Interrupt Enable
0
1
read-write
0
The assertion of IS7816[RXT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[RXT] results in the generation of an interrupt.
#1
TXTE
Transmit Threshold Exceeded Interrupt Enable
1
1
read-write
0
The assertion of IS7816[TXT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[TXT] results in the generation of an interrupt.
#1
WTE
Wait Timer Interrupt Enable
7
1
read-write
0
The assertion of IS7816[WT] does not result in the generation of an interrupt.
#0
1
The assertion of IS7816[WT] results in the generation of an interrupt.
#1
IS7816
UART 7816 Interrupt Status Register
0x1A
8
read-write
n
0x0
0x0
BWT
Block Wait Timer Interrupt
5
1
read-write
0
Block wait time (BWT) has not been violated.
#0
1
Block wait time (BWT) has been violated.
#1
CWT
Character Wait Timer Interrupt
6
1
read-write
0
Character wait time (CWT) has not been violated.
#0
1
Character wait time (CWT) has been violated.
#1
GTV
Guard Timer Violated Interrupt
2
1
read-write
0
A guard time (GT, CGT, or BGT) has not been violated.
#0
1
A guard time (GT, CGT, or BGT) has been violated.
#1
INITD
Initial Character Detected Interrupt
4
1
read-write
0
A valid initial character has not been received.
#0
1
A valid initial character has been received.
#1
RXT
Receive Threshold Exceeded Interrupt
0
1
read-write
0
The number of consecutive NACKS generated as a result of parity errors and buffer overruns is less than or equal to the value in ET7816[RXTHRESHOLD].
#0
1
The number of consecutive NACKS generated as a result of parity errors and buffer overruns is greater than the value in ET7816[RXTHRESHOLD].
#1
TXT
Transmit Threshold Exceeded Interrupt
1
1
read-write
0
The number of retries and corresponding NACKS does not exceed the value in ET7816[TXTHRESHOLD].
#0
1
The number of retries and corresponding NACKS exceeds the value in ET7816[TXTHRESHOLD].
#1
WT
Wait Timer Interrupt
7
1
read-write
0
Wait time (WT) has not been violated.
#0
1
Wait time (WT) has been violated.
#1
MA1
UART Match Address Registers 1
0x8
8
read-write
n
0x0
0x0
MA
Match Address
0
8
read-write
MA2
UART Match Address Registers 2
0x9
8
read-write
n
0x0
0x0
MA
Match Address
0
8
read-write
MODEM
UART Modem Register
0xD
8
read-write
n
0x0
0x0
RXRTSE
Receiver request-to-send enable
3
1
read-write
0
The receiver has no effect on RTS.
#0
1
RTS is deasserted if the number of characters in the receiver data register (FIFO) is equal to or greater than RWFIFO[RXWATER]. RTS is asserted when the number of characters in the receiver data register (FIFO) is less than RWFIFO[RXWATER].
#1
TXCTSE
Transmitter clear-to-send enable
0
1
read-write
0
CTS has no effect on the transmitter.
#0
1
Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent do not affect its transmission.
#1
TXRTSE
Transmitter request-to-send enable
1
1
read-write
0
The transmitter has no effect on RTS.
#0
1
When a character is placed into an empty transmitter data buffer , RTS asserts one bit time before the start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter data buffer and shift register are completely sent, including the last stop bit. (FIFO) (FIFO)
#1
TXRTSPOL
Transmitter request-to-send polarity
2
1
read-write
0
Transmitter RTS is active low.
#0
1
Transmitter RTS is active high.
#1
PFIFO
UART FIFO Parameters
0x10
8
read-write
n
0x0
0x0
RXFE
Receive FIFO Enable
3
1
read-write
0
Receive FIFO is not enabled. Buffer is depth 1. (Legacy support)
#0
1
Receive FIFO is enabled. Buffer is depth indicted by RXFIFOSIZE.
#1
RXFIFOSIZE
Receive FIFO. Buffer Depth
0
3
read-only
000
Receive FIFO/Buffer depth = 1 dataword.
#000
001
Receive FIFO/Buffer depth = 4 datawords.
#001
010
Receive FIFO/Buffer depth = 8 datawords.
#010
011
Receive FIFO/Buffer depth = 16 datawords.
#011
100
Receive FIFO/Buffer depth = 32 datawords.
#100
101
Receive FIFO/Buffer depth = 64 datawords.
#101
110
Receive FIFO/Buffer depth = 128 datawords.
#110
TXFE
Transmit FIFO Enable
7
1
read-write
0
Transmit FIFO is not enabled. Buffer is depth 1. (Legacy support).
#0
1
Transmit FIFO is enabled. Buffer is depth indicated by TXFIFOSIZE.
#1
TXFIFOSIZE
Transmit FIFO. Buffer Depth
4
3
read-only
000
Transmit FIFO/Buffer depth = 1 dataword.
#000
001
Transmit FIFO/Buffer depth = 4 datawords.
#001
010
Transmit FIFO/Buffer depth = 8 datawords.
#010
011
Transmit FIFO/Buffer depth = 16 datawords.
#011
100
Transmit FIFO/Buffer depth = 32 datawords.
#100
101
Transmit FIFO/Buffer depth = 64 datawords.
#101
110
Transmit FIFO/Buffer depth = 128 datawords.
#110
RCFIFO
UART FIFO Receive Count
0x16
8
read-only
n
0x0
0x0
RXCOUNT
Receive Counter
0
8
read-only
RWFIFO
UART FIFO Receive Watermark
0x15
8
read-write
n
0x0
0x0
RXWATER
Receive Watermark
0
8
read-write
S1
UART Status Register 1
0x4
8
read-only
n
0x0
0x0
FE
Framing Error Flag
1
1
read-only
0
No framing error detected.
#0
1
Framing error.
#1
IDLE
Idle Line Flag
4
1
read-only
0
Receiver input is either active now or has never become active since the IDLE flag was last cleared.
#0
1
Receiver input has become idle or the flag has not been cleared since it last asserted.
#1
NF
Noise Flag
2
1
read-only
0
No noise detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1 then there may be data in the receiver buffer that was received with noise.
#0
1
At least one dataword was received with noise detected since the last time the flag was cleared.
#1
OR
Receiver Overrun Flag
3
1
read-only
0
No overrun has occurred since the last time the flag was cleared.
#0
1
Overrun has occurred or the overrun flag has not been cleared since the last overrun occured.
#1
PF
Parity Error Flag
0
1
read-only
0
No parity error detected since the last time this flag was cleared. If the receive buffer has a depth greater than 1, then there may be data in the receive buffer what was received with a parity error.
#0
1
At least one dataword was received with a parity error since the last time this flag was cleared.
#1
RDRF
Receive Data Register Full Flag
5
1
read-only
0
The number of datawords in the receive buffer is less than the number indicated by RXWATER.
#0
1
The number of datawords in the receive buffer is equal to or greater than the number indicated by RXWATER at some point in time since this flag was last cleared.
#1
TC
Transmit Complete Flag
6
1
read-only
0
Transmitter active (sending data, a preamble, or a break).
#0
1
Transmitter idle (transmission activity complete).
#1
TDRE
Transmit Data Register Empty Flag
7
1
read-only
0
The amount of data in the transmit buffer is greater than the value indicated by TWFIFO[TXWATER].
#0
1
The amount of data in the transmit buffer is less than or equal to the value indicated by TWFIFO[TXWATER] at some point in time since the flag has been cleared.
#1
S2
UART Status Register 2
0x5
8
read-write
n
0x0
0x0
BRK13
Break Transmit Character Length
2
1
read-write
0
Break character is 10, 11, or 12 bits long.
#0
1
Break character is 13 or 14 bits long.
#1
MSBF
Most Significant Bit First
5
1
read-write
0
LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received after the start bit is identified as bit0.
#0
1
MSB (bit8, bit7 or bit6) is the first bit that is transmitted following the start bit, depending on the setting of C1[M] and C1[PE]. Further, the first bit received after the start bit is identified as bit8, bit7, or bit6, depending on the setting of C1[M] and C1[PE].
#1
RAF
Receiver Active Flag
0
1
read-only
0
UART receiver idle/inactive waiting for a start bit.
#0
1
UART receiver active, RxD input not idle.
#1
RWUID
Receive Wakeup Idle Detect
3
1
read-write
0
S1[IDLE] is not set upon detection of an idle character.
#0
1
S1[IDLE] is set upon detection of an idle character.
#1
RXEDGIF
RxD Pin Active Edge Interrupt Flag
6
1
read-write
0
No active edge on the receive pin has occurred.
#0
1
An active edge on the receive pin has occurred.
#1
RXINV
Receive Data Inversion
4
1
read-write
0
Receive data is not inverted.
#0
1
Receive data is inverted.
#1
SFIFO
UART FIFO Status Register
0x12
8
read-write
n
0x0
0x0
RXEMPT
Receive Buffer/FIFO Empty
6
1
read-only
0
Receive buffer is not empty.
#0
1
Receive buffer is empty.
#1
RXOF
Receiver Buffer Overflow Flag
2
1
read-write
0
No receive buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer overflow has occurred since the last time the flag was cleared.
#1
RXUF
Receiver Buffer Underflow Flag
0
1
read-write
0
No receive buffer underflow has occurred since the last time the flag was cleared.
#0
1
At least one receive buffer underflow has occurred since the last time the flag was cleared.
#1
TXEMPT
Transmit Buffer/FIFO Empty
7
1
read-only
0
Transmit buffer is not empty.
#0
1
Transmit buffer is empty.
#1
TXOF
Transmitter Buffer Overflow Flag
1
1
read-write
0
No transmit buffer overflow has occurred since the last time the flag was cleared.
#0
1
At least one transmit buffer overflow has occurred since the last time the flag was cleared.
#1
TCFIFO
UART FIFO Transmit Count
0x14
8
read-only
n
0x0
0x0
TXCOUNT
Transmit Counter
0
8
read-only
TL7816
UART 7816 Transmit Length Register
0x1F
8
read-write
n
0x0
0x0
TLEN
Transmit Length
0
8
read-write
TWFIFO
UART FIFO Transmit Watermark
0x13
8
read-write
n
0x0
0x0
TXWATER
Transmit Watermark
0
8
read-write
WF7816
UART 7816 Wait FD Register
0x1D
8
read-write
n
0x0
0x0
GTFD
FD Multiplier
0
8
read-write
WN7816
UART 7816 Wait N Register
0x1C
8
read-write
n
0x0
0x0
GTN
Guard Band N
0
8
read-write
WP7816T0
UART 7816 Wait Parameter Register
UART3
0x1B
8
read-write
n
0x0
0x0
WI
Wait Time Integer (C7816[TTYPE] = 0)
0
8
read-write
WP7816T1
UART 7816 Wait Parameter Register
UART3
0x1B
8
read-write
n
0x0
0x0
BWI
Block Wait Time Integer(C7816[TTYPE] = 1)
0
4
read-write
CWI
Character Wait Time Integer (C7816[TTYPE] = 1)
4
4
read-write
VREF
Voltage Reference
VREF
0x0
0x0
0x6
registers
n
VREFH_SC
VREF Status and Control Register
0x1
8
read-write
n
0x0
0x0
ICOMPEN
Second order curvature compensation enable
5
1
read-write
0
Disabled
#0
1
Enabled
#1
MODE_LV
Buffer Mode selection
0
2
read-write
00
Bandgap on only, for stabilization and startup
#00
01
High power buffer mode enabled
#01
10
Low-power buffer mode enabled
#10
REGEN
Regulator enable
6
1
read-write
0
Internal 1.75 V regulator is disabled.
#0
1
Internal 1.75 V regulator is enabled.
#1
VREFEN
Internal Voltage Reference enable
7
1
read-write
0
The module is disabled.
#0
1
The module is enabled.
#1
VREFST
Internal Voltage Reference stable
2
1
read-only
0
The module is disabled or not stable.
#0
1
The module is stable.
#1
VREFH_TRM
VREF Trim Register
0x0
8
read-write
n
0x0
0x0
CHOPEN
Chop oscillator enable. When set, internal chopping operation is enabled and the internal analog offset will be minimized.
6
1
read-write
0
Chop oscillator is disabled.
#0
1
Chop oscillator is enabled.
#1
TRIM
Trim bits
0
6
read-write
000000
Min
#000000
111111
Max
#111111
VREFL_TRM
VREFL TRIM Register
0x5
8
read-write
n
0x0
0x0
VREFL_EN
no description available
3
1
read-write
0
Disable
#0
1
Enable
#1
VREFL_SEL
no description available
4
1
read-write
0
Internal reference
#0
1
External reference
#1
VREFL_TRIM
no description available
0
3
read-write
WDOG
Generation 2008 Watchdog Timer
WDOG
0x0
0x0
0x18
registers
n
Watchdog
29
PRESC
Watchdog Prescaler register
0x16
16
read-write
n
0x0
0x0
PRESCVAL
no description available
8
3
read-write
REFRESH
Watchdog Refresh register
0xC
16
read-write
n
0x0
0x0
WDOGREFRESH
no description available
0
16
read-write
RSTCNT
Watchdog Reset Count register
0x14
16
read-write
n
0x0
0x0
RSTCNT
no description available
0
16
read-write
STCTRLH
Watchdog Status and Control Register High
0x0
16
read-write
n
0x0
0x0
ALLOWUPDATE
no description available
4
1
read-write
0
No further updates allowed to WDOG write-once registers.
#0
1
WDOG write-once registers can be unlocked for updating.
#1
BYTESEL
no description available
12
2
read-write
00
Byte 0 selected
#00
01
Byte 1 selected
#01
10
Byte 2 selected
#10
11
Byte 3 selected
#11
CLKSRC
no description available
1
1
read-write
0
WDOG clock sourced from LPO .
#0
1
WDOG clock sourced from alternate clock source.
#1
DBGEN
no description available
5
1
read-write
0
WDOG is disabled in CPU Debug mode.
#0
1
WDOG is enabled in CPU Debug mode.
#1
DISTESTWDOG
no description available
14
1
read-write
0
WDOG functional test mode is not disabled.
#0
1
WDOG functional test mode is disabled permanently until reset.
#1
IRQRSTEN
no description available
2
1
read-write
0
WDOG time-out generates reset only.
#0
1
WDOG time-out initially generates an interrupt. After WCT, it generates a reset.
#1
STOPEN
no description available
6
1
read-write
0
WDOG is disabled in CPU Stop mode.
#0
1
WDOG is enabled in CPU Stop mode.
#1
TESTSEL
no description available
11
1
read-write
0
Quick test. The timer runs in normal operation. You can load a small time-out value to do a quick test.
#0
1
Byte test. Puts the timer in the byte test mode where individual bytes of the timer are enabled for operation and are compared for time-out against the corresponding byte of the programmed time-out value. Select the byte through BYTESEL[1:0] for testing.
#1
TESTWDOG
no description available
10
1
read-write
WDOGEN
no description available
0
1
read-write
0
WDOG is disabled.
#0
1
WDOG is enabled.
#1
WINEN
no description available
3
1
read-write
0
Windowing mode is disabled.
#0
1
Windowing mode is enabled.
#1
STCTRLL
Watchdog Status and Control Register Low
0x2
16
read-write
n
0x0
0x0
INTFLG
no description available
15
1
read-write
TMROUTH
Watchdog Timer Output Register High
0x10
16
read-write
n
0x0
0x0
TIMEROUTHIGH
no description available
0
16
read-write
TMROUTL
Watchdog Timer Output Register Low
0x12
16
read-write
n
0x0
0x0
TIMEROUTLOW
no description available
0
16
read-write
TOVALH
Watchdog Time-out Value Register High
0x4
16
read-write
n
0x0
0x0
TOVALHIGH
no description available
0
16
read-write
TOVALL
Watchdog Time-out Value Register Low
0x6
16
read-write
n
0x0
0x0
TOVALLOW
no description available
0
16
read-write
UNLOCK
Watchdog Unlock register
0xE
16
read-write
n
0x0
0x0
WDOGUNLOCK
no description available
0
16
read-write
WINH
Watchdog Window Register High
0x8
16
read-write
n
0x0
0x0
WINHIGH
no description available
0
16
read-write
WINL
Watchdog Window Register Low
0xA
16
read-write
n
0x0
0x0
WINLOW
no description available
0
16
read-write
XBAR
Crossbar Switch
XBAR
0x0
0x0
0x24
registers
n
XBAR
31
CTRL0
Crossbar Control Register 0
0x22
16
read-write
n
0x0
0x0
DEN0
DMA Enable for XBAR_OUT0
0
1
read-write
0
DMA disabled
#0
1
DMA enabled
#1
EDGE0
Active edge for edge detection on XBAR_OUT0
2
2
read-write
00
STS0 never asserts
#00
01
STS0 asserts on rising edges of XBAR_OUT0
#01
10
STS0 asserts on falling edges of XBAR_OUT0
#10
11
STS0 asserts on rising and falling edges of XBAR_OUT0
#11
IEN0
Interrupt Enable for XBAR_OUT0
1
1
read-write
0
Interrupt disabled
#0
1
Interrupt enabled
#1
STS0
Edge detection status for XBAR_OUT0
4
1
read-write
0
Active edge not yet detected on XBAR_OUT0
#0
1
Active edge detected on XBAR_OUT0
#1
SEL0
Crossbar Select Register 0
0x0
16
read-write
n
0x0
0x0
SEL0
no description available
0
6
read-write
SEL1
no description available
8
6
read-write
SEL1
Crossbar Select Register 1
0x2
16
read-write
n
0x0
0x0
SEL2
no description available
0
6
read-write
SEL3
no description available
8
6
read-write
SEL10
Crossbar Select Register 10
0x14
16
read-write
n
0x0
0x0
SEL20
no description available
0
5
read-write
SEL21
no description available
8
5
read-write
SEL11
Crossbar Select Register 11
0x16
16
read-write
n
0x0
0x0
SEL22
no description available
0
6
read-write
SEL23
no description available
8
6
read-write
SEL12
Crossbar Select Register 12
0x18
16
read-write
n
0x0
0x0
SEL24
no description available
0
5
read-write
SEL25
no description available
8
5
read-write
SEL13
Crossbar Select Register 13
0x1A
16
read-write
n
0x0
0x0
SEL26
no description available
0
6
read-write
SEL27
no description available
8
6
read-write
SEL14
Crossbar Select Register 14
0x1C
16
read-write
n
0x0
0x0
SEL28
no description available
0
6
read-write
SEL29
no description available
8
6
read-write
SEL15
Crossbar Select Register 15
0x1E
16
read-write
n
0x0
0x0
SEL30
no description available
0
5
read-write
SEL31
no description available
8
5
read-write
SEL16
Crossbar Select Register 16
0x20
16
read-write
n
0x0
0x0
SEL32
no description available
0
6
read-write
SEL2
Crossbar Select Register 2
0x4
16
read-write
n
0x0
0x0
SEL4
no description available
0
6
read-write
SEL5
no description available
8
6
read-write
SEL3
Crossbar Select Register 3
0x6
16
read-write
n
0x0
0x0
SEL6
no description available
0
6
read-write
SEL7
no description available
8
6
read-write
SEL4
Crossbar Select Register 4
0x8
16
read-write
n
0x0
0x0
SEL8
no description available
0
6
read-write
SEL9
no description available
8
6
read-write
SEL5
Crossbar Select Register 5
0xA
16
read-write
n
0x0
0x0
SEL10
no description available
0
6
read-write
SEL11
no description available
8
6
read-write
SEL6
Crossbar Select Register 6
0xC
16
read-write
n
0x0
0x0
SEL12
no description available
0
6
read-write
SEL13
no description available
8
6
read-write
SEL7
Crossbar Select Register 7
0xE
16
read-write
n
0x0
0x0
SEL14
no description available
0
6
read-write
SEL15
no description available
8
6
read-write
SEL8
Crossbar Select Register 8
0x10
16
read-write
n
0x0
0x0
SEL16
no description available
0
6
read-write
SEL17
no description available
8
6
read-write
SEL9
Crossbar Select Register 9
0x12
16
read-write
n
0x0
0x0
SEL18
no description available
0
6
read-write
SEL19
no description available
8
6
read-write